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[34.147.70.202]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c504a663f3bsm213970866b.72.2026.11.11.00.57.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2026 00:57:19 -0800 (PST) Date: Wed, 11 Nov 2026 09:57:15 +0100 From: =?utf-8?Q?Pierre-Cl=C3=A9ment?= Tosi To: Catalin Marinas Cc: Will Deacon , Mark Rutland , Vincenzo Frascino , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Peter Collingbourne , stable@vger.kernel.org Subject: Re: [PATCH 01/24] arm64: Fix lazy TCO clear when enabling user MTE Message-ID: References: <20261107-mte-kasan-split-v1-0-d84ea5f30f94@google.com> <20261107-mte-kasan-split-v1-1-d84ea5f30f94@google.com> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261111_005722_181798_12A8999B X-CRM114-Status: GOOD ( 19.75 ) X-Spam-Score: -17.6 (-----------------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-18.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIMWL_WL_MED,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Hi Catalin, On Tue, Nov 10, 2026 at 06:33:20PM +0000, Catalin Marinas wrote: > On Sat, Nov 07, 2026 at 04:36:07PM +0100, Pierre-Clément Tosi wrote: > > On kernel entry from EL0 with HW KASAN inactive and user MTE disabled or > > in async mode, mte_disable_tco_entry() leaves PSTATE.TCO set to avoid an > > expensive write, as it assumes that EL1 tag checks are not needed. > > > > However, if the thread is in the process of enabling sync or asymm MTE, > > set_mte_ctrl() updates SCTLR_EL1.TCF0 without clearing PSTATE.TCO! As a > > result, kernel uaccesses miss tag faults until the next context switch. > > Nit: next context switch or another syscall. I think this makes it > clearer that the only potential missed tag accesses after the prctl() is > a signal frame write as we don't have other uaccesses. > > > Clear TCO in set_mte_ctrl() immediately after setting the task's SCTLR. > > > > Cc: Peter Collingbourne > > Cc: stable@vger.kernel.org > > Fixes: 38ddf7dafaea ("arm64: mte: avoid clearing PSTATE.TCO on entry unless necessary") > > Signed-off-by: Pierre-Clément Tosi > > The patch is correct but I wonder whether we need a cc stable. > > Reviewed-by: Catalin Marinas Thanks for your review. I'm happy to drop the cc in the next version. The rationale was that this fixed an unexpected userspace-visible kernel behavior and closed a window during which tag checks were not performed, which _could_ be a concern when userspace enables MTE for security. I can see how this doesn't make a strong case for backporting. -- Pierre