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Received: by smtp.zohomail.com with SMTPS id 1794501201770774.608247615585; Thu, 12 Nov 2026 08:33:21 -0800 (PST) Received: by venus (Postfix, from userid 1000) id EA777180570; Thu, 12 Nov 2026 17:33:16 +0100 (CET) Date: Thu, 12 Nov 2026 17:33:16 +0100 From: Sebastian Reichel To: aiyengar1990@gmail.com Cc: Will Deacon , Robin Murphy , "Joerg Roedel (AMD)" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Pranjal Shrivastava , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, Shawn Lin , Simon Xue , Finley Xiao Subject: Re: [PATCH v2 4/4] arm64: dts: rockchip: Add the reset of the RK3588 PCIe SMMU Message-ID: References: <20261112-smmu-v3-pcie-pd-v2-0-3a77bbb6b2c4@gmail.com> <20261112-smmu-v3-pcie-pd-v2-4-3a77bbb6b2c4@gmail.com> X-Archived-By: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; 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protected-headers=v1; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: Re: [PATCH v2 4/4] arm64: dts: rockchip: Add the reset of the RK3588 PCIe SMMU MIME-Version: 1.0 Hi, On Thu, Nov 12, 2026 at 08:20:25AM +0000, Arun Iyengar via B4 Relay wrote: > From: Arun Iyengar >=20 > The MMU-600 for the PCIe controllers (mmu600_pcie) has a reset line in > the CRU, SRST_A_MMU_PCIE, which its node does not describe. Add it, so > that the node describes both the clock and the reset of the MMU-600. >=20 > Signed-off-by: Arun Iyengar > --- squash this into the previous commit. -- Sebastian > arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 1 + > 1 file changed, 1 insertion(+) >=20 > diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/b= oot/dts/rockchip/rk3588-base.dtsi > index dfed34a8aa57..45c1bb335447 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi > @@ -560,6 +560,7 @@ mmu600_pcie: iommu@fc900000 { > ; > interrupt-names =3D "eventq", "gerror", "priq", "cmdq-sync"; > clocks =3D <&cru ACLK_MMU_PCIE>; > + resets =3D <&cru SRST_A_MMU_PCIE>; > #iommu-cells =3D <1>; > }; > =20 >=20 > --=20 > 2.55.0 >=20 >=20 --plo7cdziw5qygczc Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE72YNB0Y/i3JqeVQT2O7X88g7+poFAmr16kgACgkQ2O7X88g7 +ppxMRAAj3Ltv4ErhZU0f3wZhYPQJhx+mkY3nlU/L6SyJGdIyiP+f5sNRq1yS3PC uFjSX4M0IV7s6bymiCkx5mimtXcqWnpJZREgT5rE/pn6qA2oEbSvaV71cPBghWMp cMCpa6RU7UME/Aj2laC7m+FhA9n6HUGYRchQQbSmd0y+bh6QJq2eGNstI0+1Jl8a xgKEyVomPUWe6U+/gvO+f5huDrx8A6AXYmvP/u+1W2pIYcl7khGjb3RimLjhN//o IlsoSB3yFBwQsKDJnQBlaCukfQfCaMRFjH6zvIsFMiic2wdLKWTdnDlsFwXXI3HP Ckxh7FkdAZmT0FhKm+AkHBschqSqzZTfrHfhy9SrOZgXWOTz1jQE9nIurWtjnyco 0BtZjwgYCXWMIEOfV+YSrga4BvooysTtTm9/5FBy/YxY1LWjVMYf/73np8yJ4LYC yiaPA2M3PfhrK3Pqwany/VxcqF0mgh9wMynwWMmJQXesRv+ECPHtLz+dZ6Ib2pcs s+rN0hjEsm8tRsTN38r1n0MTlfMAsSBi2Ms3vTmj2v/jPsAwhb2mpPgJwEP8+k8j cN3vrq1sFgYJMee561K3JiUcpm0aCN55NAuTaQ9fOpV8ow4xNn4vrgh+EvjU+LTQ YY8DlesoqyZuG6FPd2GvJ5jpRLK2IJtMp+Ao116jHyFzg/oN3UI= =VZSZ -----END PGP SIGNATURE----- --plo7cdziw5qygczc--