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Received: by smtp.zohomail.com with SMTPS id 1794507361217249.80952065575377; Thu, 12 Nov 2026 10:16:01 -0800 (PST) Received: by venus (Postfix, from userid 1000) id 71311180570; Thu, 12 Nov 2026 19:15:56 +0100 (CET) Date: Thu, 12 Nov 2026 19:15:56 +0100 From: Sebastian Reichel To: Ulf Hansson Cc: Leonard Lausen , ulfh@kernel.org, heiko@sntech.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, detlev.casanova@collabora.com, finley.xiao@rock-chips.com, zhangqing@rock-chips.com, inindev@gmail.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, gahing@gahingwoo.com Subject: Re: [PATCH 1/2] pmdomain: rockchip: Manage the RK3576 GPU domain supply Message-ID: References: <20261019092417.391522-1-leonard@lausen.nl> <20261019092417.391522-2-leonard@lausen.nl> X-Archived-By: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="5zcx2h2fm6qurjpz" Content-Disposition: inline In-Reply-To: X-Zoho-Virus-Status: 1 X-Zoho-AV-Stamp: zmail-av-0.2.13.1.5.4/294.497.36 X-ZohoMailClient: External X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261112_101610_771696_FD2F6FFC X-CRM114-Status: GOOD ( 28.09 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 --5zcx2h2fm6qurjpz Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: Re: [PATCH 1/2] pmdomain: rockchip: Manage the RK3576 GPU domain supply MIME-Version: 1.0 Hi, On Thu, Nov 12, 2026 at 04:19:58PM +0100, Ulf Hansson wrote: > On Mon, Oct 19, 2026 at 11:24=E2=80=AFAM Leonard Lausen wrote: > > > > On the NanoPi M5, boot hangs during Panfrost initialization. Before this > > fix, booting required blacklisting Panfrost on the kernel command line. > > Loading Panfrost after boot reports a GPU power-domain acknowledgment > > timeout: > > > > failed to get ack on domain 'gpu', val=3D0x113ff > > > > Add regulator support to the RK3576 domain descriptors and mark the GPU > > domain as regulator-dependent. This lets the existing Rockchip > > power-domain regulator handling manage the GPU domain supply. > > > > A corresponding domain-supply property is needed in the board DT. > > > > The regulator-capable descriptors are based on the regulator support in > > Jiaxing Hu's pending RK3576 NPU enablement series, without its NPU sett= le > > delay changes. > > > > Link: https://lore.kernel.org/all/20260924102135.92217-10-gahing@gahing= woo.com/ > > Fixes: cfee1b507758 ("pmdomain: rockchip: Add support for RK3576 SoC") > > Signed-off-by: Leonard Lausen >=20 > So this should be applied as a fix and tagged for stable kernels, right? Maybe like this, considering it requires regulator support, which landed in db6df2e3fc16 ("pmdomain: rockchip: add regulator support"): Cc: stable@vger.kernel.org # v6.15+ Greetings, -- Sebastian >=20 > Kind regards > Uffe >=20 > > > > --- > > drivers/pmdomain/rockchip/pm-domains.c | 10 +++++++--- > > 1 file changed, 7 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/= rockchip/pm-domains.c > > index e193f978d5f35..b41f9fcb62bfe 100644 > > --- a/drivers/pmdomain/rockchip/pm-domains.c > > +++ b/drivers/pmdomain/rockchip/pm-domains.c > > @@ -176,41 +176,42 @@ struct rockchip_pmu { > > .mem_offset =3D m_offset, \ > > .mem_status_mask =3D (m_status), \ > > .repair_status_mask =3D (r_status), \ > > .req_offset =3D r_offset, \ > > .req_w_mask =3D (req) << 16, \ > > .req_mask =3D (req), \ > > .idle_mask =3D (idle), \ > > .ack_mask =3D (ack), \ > > .active_wakeup =3D wakeup, \ > > .need_regulator =3D regulator, \ > > } > > > > -#define DOMAIN_M_O_R_G(_name, p_offset, pwr, status, m_offset, m_statu= s, r_status, r_offset, req, idle, ack, g_mask, wakeup) \ > > +#define DOMAIN_M_O_R_G(_name, p_offset, pwr, status, m_offset, m_statu= s, r_status, r_offset, req, idle, ack, g_mask, wakeup, regulator) \ > > { \ > > .name =3D _name, \ > > .pwr_offset =3D p_offset, \ > > .pwr_w_mask =3D (pwr) << 16, \ > > .pwr_mask =3D (pwr), \ > > .status_mask =3D (status), \ > > .mem_offset =3D m_offset, \ > > .mem_status_mask =3D (m_status), \ > > .repair_status_mask =3D (r_status), \ > > .req_offset =3D r_offset, \ > > .req_w_mask =3D (req) << 16, \ > > .req_mask =3D (req), \ > > .idle_mask =3D (idle), \ > > .clk_ungate_mask =3D (g_mask), \ > > .ack_mask =3D (ack), \ > > .active_wakeup =3D wakeup, \ > > + .need_regulator =3D regulator, \ > > } > > > > #define DOMAIN_M_R(_name, pwr, status, req, idle, ack, wakeup, regulat= or) \ > > { \ > > .name =3D _name, \ > > .pwr_w_mask =3D (pwr) << 16, \ > > .pwr_mask =3D (pwr), \ > > .status_mask =3D (status), \ > > .req_w_mask =3D (req) << 16, \ > > .req_mask =3D (req), \ > > .idle_mask =3D (idle), \ > > .ack_mask =3D (ack), \ > > @@ -250,25 +251,28 @@ struct rockchip_pmu { > > DOMAIN(name, pwr, status, req, req, req, wakeup) > > > > #define DOMAIN_RK3528(name, pwr, req) \ > > DOMAIN_M(name, pwr, pwr, req, req, req, false) > > > > #define DOMAIN_RK3562(name, pwr, req, g_mask, mem, wakeup) = \ > > DOMAIN_M_G_SD(name, pwr, pwr, req, req, req, g_mask, mem, wakeu= p, false) > > > > #define DOMAIN_RK3568(name, pwr, req, wakeup, regulator) = \ > > DOMAIN_M_R(name, pwr, pwr, req, req, req, wakeup, regulator) > > > > #define DOMAIN_RK3576(name, p_offset, pwr, status, r_status, r_offset,= req, idle, g_mask, wakeup) \ > > - DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_stat= us, r_offset, req, idle, idle, g_mask, wakeup) > > + DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_stat= us, r_offset, req, idle, idle, g_mask, wakeup, false) > > + > > +#define DOMAIN_RK3576_R(name, p_offset, pwr, status, r_status, r_offse= t, req, idle, g_mask, wakeup) \ > > + DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_stat= us, r_offset, req, idle, idle, g_mask, wakeup, true) > > > > /* > > * Dynamic Memory Controller may need to coordinate with us -- see > > * rockchip_pmu_block(). > > * > > * dmc_pmu_mutex protects registration-time races, so DMC driver doesn= 't try to > > * block() while we're initializing the PMU. > > */ > > static DEFINE_MUTEX(dmc_pmu_mutex); > > static struct rockchip_pmu *dmc_pmu; > > > > /* > > @@ -1323,25 +1327,25 @@ static const struct rockchip_domain_info rk3576= _pm_domains[] =3D { > > [RK3576_PD_VOP] =3D DOMAIN_RK3576("vop", 0x0, BIT(11= ), 0, BIT(11), 0x0, 0x6000, 0x6000, 0x6000, false), > > [RK3576_PD_VO1] =3D DOMAIN_RK3576("vo1", 0x0, BIT(14= ), 0, BIT(14), 0x0, BIT(12), BIT(12), 0x7000, false), > > [RK3576_PD_VO0] =3D DOMAIN_RK3576("vo0", 0x0, BIT(15= ), 0, BIT(15), 0x0, BIT(11), BIT(11), 0x6800, false), > > [RK3576_PD_USB] =3D DOMAIN_RK3576("usb", 0x4, BIT(0)= , 0, BIT(16), 0x0, BIT(10), BIT(10), 0x6400, true), > > [RK3576_PD_VI] =3D DOMAIN_RK3576("vi", 0x4, BIT(1)= , 0, BIT(17), 0x0, BIT(9), BIT(9), BIT(9), false), > > [RK3576_PD_VEPU0] =3D DOMAIN_RK3576("vepu0", 0x4, BIT(2)= , 0, BIT(18), 0x0, BIT(7), BIT(7), 0x280, false), > > [RK3576_PD_VEPU1] =3D DOMAIN_RK3576("vepu1", 0x4, BIT(3)= , 0, BIT(19), 0x0, BIT(8), BIT(8), BIT(8), false), > > [RK3576_PD_VDEC] =3D DOMAIN_RK3576("vdec", 0x4, BIT(4)= , 0, BIT(20), 0x0, BIT(6), BIT(6), BIT(6), false), > > [RK3576_PD_VPU] =3D DOMAIN_RK3576("vpu", 0x4, BIT(5)= , 0, BIT(21), 0x0, BIT(5), BIT(5), BIT(5), false), > > [RK3576_PD_NPUTOP] =3D DOMAIN_RK3576("nputop", 0x4, BIT(6)= , 0, BIT(22), 0x0, 0x18, 0x18, 0x18, false), > > [RK3576_PD_NPU0] =3D DOMAIN_RK3576("npu0", 0x4, BIT(7)= , 0, BIT(23), 0x0, BIT(1), BIT(1), 0x1a, false), > > [RK3576_PD_NPU1] =3D DOMAIN_RK3576("npu1", 0x4, BIT(8)= , 0, BIT(24), 0x0, BIT(2), BIT(2), 0x1c, false), > > - [RK3576_PD_GPU] =3D DOMAIN_RK3576("gpu", 0x4, BIT(9)= , 0, BIT(25), 0x0, BIT(0), BIT(0), BIT(0), false), > > + [RK3576_PD_GPU] =3D DOMAIN_RK3576_R("gpu", 0x4, BIT(9)= , 0, BIT(25), 0x0, BIT(0), BIT(0), BIT(0), false), > > }; > > > > static const struct rockchip_domain_info rk3588_pm_domains[] =3D { > > [RK3588_PD_GPU] =3D DOMAIN_RK3588("gpu", 0x0, BIT(0= ), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false, true), > > [RK3588_PD_NPU] =3D DOMAIN_RK3588("npu", 0x0, BIT(1= ), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false, true), > > [RK3588_PD_VCODEC] =3D DOMAIN_RK3588("vcodec", 0x0, BIT(2= ), BIT(2), 0x0, 0, 0, 0x0, 0, 0, false, true), > > [RK3588_PD_NPUTOP] =3D DOMAIN_RK3588("nputop", 0x0, BIT(3= ), 0, 0x0, BIT(11), BIT(2), 0x0, BIT(1), BIT(1), false, false), > > [RK3588_PD_NPU1] =3D DOMAIN_RK3588("npu1", 0x0, BIT(4= ), 0, 0x0, BIT(12), BIT(3), 0x0, BIT(2), BIT(2), false, false), > > [RK3588_PD_NPU2] =3D DOMAIN_RK3588("npu2", 0x0, BIT(5= ), 0, 0x0, BIT(13), BIT(4), 0x0, BIT(3), BIT(3), false, false), > > [RK3588_PD_VENC0] =3D DOMAIN_RK3588("venc0", 0x0, BIT(6= ), 0, 0x0, BIT(14), BIT(5), 0x0, BIT(4), BIT(4), false, false), > > [RK3588_PD_VENC1] =3D DOMAIN_RK3588("venc1", 0x0, BIT(7= ), 0, 0x0, BIT(15), BIT(6), 0x0, BIT(5), BIT(5), false, false), > > [RK3588_PD_RKVDEC0] =3D DOMAIN_RK3588("rkvdec0", 0x0, BIT(8= ), 0, 0x0, BIT(16), BIT(7), 0x0, BIT(6), BIT(6), false, false), > > -- > > 2.47.3 > > >=20 --5zcx2h2fm6qurjpz Content-Type: application/pgp-signature; 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