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Fri, 13 Nov 2026 11:01:07 -0800 Received: from nvidia.com (10.127.8.14) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.56 via Frontend Transport; Fri, 13 Nov 2026 11:01:06 -0800 Date: Fri, 13 Nov 2026 11:01:04 -0800 From: Nicolin Chen To: "Peng Fan (OSS)" , Robin Murphy CC: Will Deacon , "Joerg Roedel (AMD)" , Jean-Philippe Brucker , Jason Gunthorpe , Thierry Reding , Krishna Reddy , Jonathan Hunter , , , , , Peng Fan Subject: Re: [PATCH RFC v8 4/9] iommu/arm-smmu-v3: Use a per-domain CD table for non-PASID streams Message-ID: References: <20261113-b4-smmu-shared-sid-ver8-v8-0-587307a77f3a@nxp.com> <20261113-b4-smmu-shared-sid-ver8-v8-4-587307a77f3a@nxp.com> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20261113-b4-smmu-shared-sid-ver8-v8-4-587307a77f3a@nxp.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS4PEPF000001C2:EE_|CYYPR12MB8989:EE_ X-MS-Office365-Filtering-Correlation-Id: 9e8e376b-ed0f-47f8-c729-08df41c3e68b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|23010399003|1800799024|82310400026|36860700016|10067099003|4143699003|11063799006|56012099006|261026121527099003|261022105027099003|261026140227099003|261028144727099003|261021135927099003|261009223027099003|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: fYBD6h5y8Ilp8qaOB/RFKma+mGYXn7deM0nC4WQBlqeeaPswSbIneKPj8hV1NK/X8nPCI9lQRhxPQPVspUhXE/ry9Udianh34uCyQ0B6y0cBMt5xSniWsJicZDJBQ+ftYJkfwJPc8YDfkw4jeviF13bMl2yLsRuUBedBFbugcna7U4x82qnq21tRLUl0hzsSjzyouNrQbJXuUodJMZH1i1UOR7WJhAhOYM/D/KeYjG7hcgT4a1uXW12OTQBeh3JT0letDEwsg324zi9u6g0/P5fsYUmGY3ZHSJpsYuuRywIqk+oXLHIt5Nmpb9EkI5AE5cErlA6DAz0rFPwz9IFYxjMjRv2J3Gd29W6abh0W9C1Qzf6Q7ny4B4rFcbiy+s63sX8fAoiTaKxKL8zIWAnyTz1+FffxPwuPD55Usz5JZgfMl1d+rmiloaXF91+AhGUa X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Nov 2026 20:22:55.1070 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9e8e376b-ed0f-47f8-c729-08df41c3e68b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS4PEPF000001C2.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8989 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261113_122311_577757_6C4F8651 X-CRM114-Status: GOOD ( 26.63 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-10.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Fri, Nov 13, 2026 at 09:27:16PM +0800, Peng Fan (OSS) wrote: > +static int arm_smmu_alloc_cd_ptr_l2(struct arm_smmu_master *master, u32 ssid) > +{ > + struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table; > + unsigned int idx = arm_smmu_cdtab_l1_idx(ssid); > + struct arm_smmu_cdtab_l2 **l2ptr = &cd_table->l2.l2ptrs[idx]; > + dma_addr_t l2ptr_dma; > + > + if (*l2ptr) > + return 0; > + > + *l2ptr = dma_alloc_coherent(master->smmu->dev, sizeof(**l2ptr), > + &l2ptr_dma, GFP_KERNEL); > + if (!*l2ptr) > + return -ENOMEM; > + > + arm_smmu_write_cd_l1_desc(&cd_table->l2.l1tab[idx], l2ptr_dma); > + /* An invalid L1CD can be cached */ > + arm_smmu_sync_cd(master, ssid, false); > + return 0; > +} This patch is a bit too big. Move this into a prep patch please. > @@ -1793,9 +1801,22 @@ static int arm_smmu_alloc_cd_tables(struct arm_smmu_device *smmu, > > static int arm_smmu_master_alloc_cd_tables(struct arm_smmu_master *master) > { > - return arm_smmu_alloc_cd_tables(master->smmu, &master->cd_table, > - master->ssid_bits, > - master->ats_always_on); > + int ret; > + > + ret = arm_smmu_alloc_cd_tables(master->smmu, &master->cd_table, > + master->ssid_bits, > + master->ats_always_on); > + if (ret) > + return ret; > + > + if (master->cd_table.s1fmt == STRTAB_STE_0_S1FMT_64K_L2) { > + ret = arm_smmu_alloc_cd_ptr_l2(master, IOMMU_NO_PASID); > + if (ret) { > + arm_smmu_free_cd_tables(master->smmu, &master->cd_table); > + memset(&master->cd_table, 0, sizeof(master->cd_table)); > + } It'd be helpful to have a line of inline comments stating why this is needed here. > @@ -1830,6 +1851,12 @@ static void arm_smmu_free_cd_tables(struct arm_smmu_device *smmu, > } > } > > +static int arm_smmu_domain_alloc_cd_tables(struct arm_smmu_domain *smmu_domain) > +{ > + return arm_smmu_alloc_cd_tables(smmu_domain->smmu, Hmm, that's not good. We are trying to decouple smmu_domain from an SMMU instance so that one smmu_domain can be shared across multiple SMMU instances. Tying one instance to a domain is apparently going against it.. Instead, we would need an {smmu, cd_table, refcount} list. And it'd make thing more complicated than letting master own CD table as-is. Not sure if it's still worth doing so. Robin? > @@ -3971,15 +4058,23 @@ int arm_smmu_set_pasid(struct arm_smmu_master *master, > if (smmu_domain->smmu != master->smmu) > return -EINVAL; > > - if (!master->cd_table.in_ste && > + if (!((sid_domain->type & __IOMMU_DOMAIN_PAGING) && > + to_smmu_domain(sid_domain)->stage == ARM_SMMU_DOMAIN_S1) && > sid_domain->type != IOMMU_DOMAIN_IDENTITY && > sid_domain->type != IOMMU_DOMAIN_BLOCKED) > return -EINVAL; > > + first = !arm_smmu_ssids_in_use(&master->cd_table); > cdptr = arm_smmu_alloc_cd_ptr(master, pasid); > if (!cdptr) > return -ENOMEM; > > + if (first) { > + cd0ptr = arm_smmu_master_get_cd_ptr(master, IOMMU_NO_PASID); > + if (WARN_ON(!cd0ptr)) > + return -ENXIO; You don't need "first" at all, given ... > mutex_lock(&arm_smmu_asid_lock); > ret = arm_smmu_attach_prepare(&state, &smmu_domain->domain); > if (ret) { > @@ -3995,7 +4090,30 @@ int arm_smmu_set_pasid(struct arm_smmu_master *master, > cd->data[0] |= cpu_to_le64( > FIELD_PREP(CTXDESC_CD_0_ASID, smmu_domain->cd.asid)); > > + /* > + * The private CD table is taking over the STE now. Make sure its > + * default substream matches the RID domain before the STE points at > + * it, since non-PASID traffic follows CD[0]. > + */ > + if (first) { > + if ((sid_domain->type & __IOMMU_DOMAIN_PAGING) && > + to_smmu_domain(sid_domain)->stage == ARM_SMMU_DOMAIN_S1) { > + struct arm_smmu_cd cd0; > + > + arm_smmu_make_s1_cd(&cd0, master, > + to_smmu_domain(sid_domain)); > + arm_smmu_write_cd_entry(master, IOMMU_NO_PASID, > + cd0ptr, &cd0); ... there is only one place using the cd0ptr. > @@ -4015,35 +4133,61 @@ static int arm_smmu_blocking_set_dev_pasid(struct iommu_domain *new_domain, [...] > /* > - * When the last user of the CD table goes away downgrade the STE back > - * to a non-cd_table one, by re-attaching its sid_domain. > + * When the last user of the CD table goes away, switch the STE back to > + * the RID domain's CD table (S1) or to the native bypass/abort STE > + * (identity/blocked). Do not call attach_dev() for an S1 paging domain: > + * this is a teardown path where allocation failures cannot be > + * propagated. The private CD table is kept allocated for reuse and > + * freed when the device goes away. > */ > if (!arm_smmu_ssids_in_use(&master->cd_table)) { > struct iommu_domain *sid_domain = > iommu_driver_get_domain_for_dev(master->dev); > - bool ats_always_on = master->ats_always_on && > - sid_domain->type != IOMMU_DOMAIN_BLOCKED; > - bool downgrade = sid_domain->type == IOMMU_DOMAIN_IDENTITY || > - sid_domain->type == IOMMU_DOMAIN_BLOCKED; > > - if (!ats_always_on && downgrade) > - sid_domain->ops->attach_dev(sid_domain, dev, > - sid_domain); > + if (!master->ats_always_on || > + sid_domain->type == IOMMU_DOMAIN_BLOCKED) { > + if ((sid_domain->type & __IOMMU_DOMAIN_PAGING) && > + to_smmu_domain(sid_domain)->stage == > + ARM_SMMU_DOMAIN_S1) { > + struct arm_smmu_ste ste; > + struct arm_smmu_domain *sid_smmu_domain = > + to_smmu_domain(sid_domain); > + > + mutex_lock(&arm_smmu_asid_lock); > + arm_smmu_make_cdtable_ste( > + &ste, master, &sid_smmu_domain->cd_table, > + master->ats_enabled, > + STRTAB_STE_1_S1DSS_SSID0); > + arm_smmu_install_ste_for_dev(master, &ste); > + mutex_unlock(&arm_smmu_asid_lock); > + } else if (sid_domain->type == IOMMU_DOMAIN_IDENTITY || > + sid_domain->type == IOMMU_DOMAIN_BLOCKED) { > + ret = sid_domain->ops->attach_dev(sid_domain, dev, > + sid_domain); I commented in v7 that attach_dev shouldn't propagate the ret.. Although your patch-9 clean it back to the right form, I think there should be a way to prepare things cleanly so that you can make a change here in one shot. Nicolin