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Fri, 13 Nov 2026 11:09:32 -0800 Received: from nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.56 via Frontend Transport; Fri, 13 Nov 2026 11:09:31 -0800 Date: Fri, 13 Nov 2026 11:09:29 -0800 From: Nicolin Chen To: "Peng Fan (OSS)" CC: Will Deacon , Robin Murphy , "Joerg Roedel (AMD)" , Jean-Philippe Brucker , Jason Gunthorpe , Thierry Reding , Krishna Reddy , Jonathan Hunter , , , , , Peng Fan Subject: Re: [PATCH RFC v8 7/9] iommu/arm-smmu-v3: Wire up shared-SID STE ordering and feature gating Message-ID: References: <20261113-b4-smmu-shared-sid-ver8-v8-0-587307a77f3a@nxp.com> <20261113-b4-smmu-shared-sid-ver8-v8-7-587307a77f3a@nxp.com> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20261113-b4-smmu-shared-sid-ver8-v8-7-587307a77f3a@nxp.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MW2PEPF00014677:EE_|DM4PR12MB6280:EE_ X-MS-Office365-Filtering-Correlation-Id: 98b3e7ca-6bf1-4aef-5551-08df41ca656d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|82310400026|7416014|376014|23010399003|18002099003|22082099003|261009223027099003|11063799006|5023799004|261102123227099003|4143699003|56012099006|10067099003|261028144727099003|261026140227099003|261022105027099003|261026121527099003|261022075727099003|261021121427099003|261021135927099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: fDtfDvuBF99MsVwzDXO/tvaRdrl6A5W15uHqxVTuoe4cNtzYUqqzY+UUB3M9RIk6mZu4pknUdSC7CkZlusVfKdIupRx3ekx01uB8UZP1lxXYPV0C4fwNoPnsAV2Wn0hP/Ph2ALOYGXB661AnvEhYXGRs2938+SidHE9GnTVX9n7AohkT4VLi/22jSj/UZtdV2T2oHEOtZKkgfaPNdwucRm5FfmxFShbESEz/D9SbeZu8ZzOKxgditydIDpnlcRSdqftjkdy8Kud3Ez9iPsvP+mXE+PFVy+WiPAB2/G4+kddB5e1Z8qQ8tcC7JjY/yYpw8uHm7z7M6/baIEmx1l0fe9NWKoAmYt5+68T3ww91yV4IyA69vP1Te8StYpa7cK3uYkTDqwOjWGyZwUsIbjHAcC3Bq4TUdRF/cDsdQvhC0LAk/7+OmKZICYUEu98VzLa5 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Nov 2026 21:09:24.9719 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 98b3e7ca-6bf1-4aef-5551-08df41ca656d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MW2PEPF00014677.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6280 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261113_130942_988967_D3DE9448 X-CRM114-Status: GOOD ( 14.88 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-10.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Fri, Nov 13, 2026 at 09:27:19PM +0800, Peng Fan (OSS) wrote: > From: Peng Fan > > With the per-domain CD table, every non-PASID sharer of a SID builds the > same normal-domain STE: same S1ContextPtr, S1DSS and S1CDMAX. Disable > PASID and ATS for shared SIDs as well, so the remaining STE fields are > common too, and let any sharer program the STE. This also handles the > case where one device's driver attaches before the stream owner's driver: > the first attach now installs a valid STE instead of leaving the boot or > firmware STE in place. > > A per-device release must not abort a shared STE while other sharers > remain, otherwise it would break their ongoing DMA. Use a dedicated > release domain instead of inferring release from the STE contents: > group-wide BLOCKED attaches still program the abort STE, while the > release domain skips writes until the last master no longer shares the > SID. > > Disable SVA, PASID, vSMMU nesting, ATS and IOPF/stall for shared-SID > masters since all of them require an unambiguous SID-to-device mapping. > Reject sharing at insert_master() time if either master wants stalling, > if the incoming master requires ATS, if the existing master has PASID, > ATS or vSMMU state enabled, or if a PCI and a non-PCI master would share > the SID. Other ATS-capable shared devices have their ATS capability > prepared, but ATS is not enabled while the SID is shared. > > Resolve stall_enabled before insert_master(), and use master->stall_enabled > directly for CD.S, STE.S1STALLD and STE.S2S. A shared master can never > have stalling enabled. > > Add arm_smmu_master_shares_sid() as an inline helper in arm-smmu-v3.h so > that arm-smmu-v3-sva.c and arm-smmu-v3-iommufd.c can use it without > repeating the list_empty() pattern. > > Signed-off-by: Peng Fan I am asking a bigger question in PATCH-4 for Robin to confirm, yet Sashiko gave a few scary findings against patch 7-9. Would you please run Sashiko locally and address them as much as possible, before sending a new version? Nicolin