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Sat, 15 Nov 2025 01:10:42 -0800 (PST) Received: from geday ([2804:7f2:800b:a07a::dead:c001]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2a49d695821sm22796380eec.0.2025.11.15.01.10.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Nov 2025 01:10:42 -0800 (PST) Date: Sat, 15 Nov 2025 06:10:36 -0300 From: Geraldo Nascimento To: linux-rockchip@lists.infradead.org Cc: Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski , Conor Dooley , Johan Jonker , Geraldo Nascimento , Dragan Simic Subject: [PATCH 2/3] PCI: rockchip-host: comment danger of 5.0 GT/s speed Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251115_011043_581272_5C984671 X-CRM114-Status: GOOD ( 12.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org According to Rockchip sources, there is grave danger in enabling 5.0 GT/s speed for this core. Add a comment documenting that danger and discouraging end-users from forcing higher speed through DT changes. Link: https://lore.kernel.org/all/ffd05070-9879-4468-94e3-b88968b4c21b@rock-chips.com/ Reported-by: Shawn Lin Signed-off-by: Geraldo Nascimento --- drivers/pci/controller/pcie-rockchip-host.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c index ee1822ca01db..7e6ff76466b7 100644 --- a/drivers/pci/controller/pcie-rockchip-host.c +++ b/drivers/pci/controller/pcie-rockchip-host.c @@ -332,6 +332,11 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip) /* * Enable retrain for gen2. This should be configured only after * gen1 finished. + * + * According to Rockchip this path is dangerous and may lead to + * catastrophic failure. Even if the odds are small, users are + * still discouraged to engage the corresponding DT option. + * */ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL2); status &= ~PCI_EXP_LNKCTL2_TLS; -- 2.49.0