From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B266BC4CEC9 for ; Tue, 17 Sep 2019 09:31:51 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8466720862 for ; Tue, 17 Sep 2019 09:31:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="ZoVvBoOR" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8466720862 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=qxZ2c3e4iSv99kmJ3TlmHdBH/Sa+56mF6NYojiyRIPU=; b=ZoVvBoOR9diGV2A3Y0B9Tf8Di lN548h4rROL6oJ4wAyxSxkhJTIdWZb5g7s3/xXqbX/5lTrGQfmm5tlmt3MTIVkdwKntyQ0kHRmiPV BCp77PhKdirmgrhn6ebLAaaCEJ1/Yfw/hwx2iMcqlslM6zayPk8YtDS9fsU3MUrnk5IBfIMoU5HkT Ypngx7zP0bqNoJOAYns+ldnIyS/T8f1S2SPd6ZHVddMiBpckyD1x0OCqNpedfhATSxhydG32vyt21 YbNmu//Uji6Em5U0dmMSQYH65+OC4xEpWOwHDERMZUiC4SjqNbi30g4EQpeuBrVC8qgVhly4Si8Uh 9jxtQEHaA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iA9pv-0002u8-6F; Tue, 17 Sep 2019 09:31:51 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iA9ps-0002tf-Sh for linux-arm-kernel@lists.infradead.org; Tue, 17 Sep 2019 09:31:50 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8EB1528; Tue, 17 Sep 2019 02:31:47 -0700 (PDT) Received: from dawn-kernel.cambridge.arm.com (unknown [10.1.197.116]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A414A3F59C; Tue, 17 Sep 2019 02:31:46 -0700 (PDT) Subject: Re: [PATCH v2 03/11] coresight: etm4x: Add missing API to set EL match on address filters To: mike.leach@linaro.org, mathieu.poirier@linaro.org, linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org, linux-doc@vger.kernel.org References: <20190829213321.4092-1-mike.leach@linaro.org> <20190829213321.4092-4-mike.leach@linaro.org> From: Suzuki K Poulose Message-ID: Date: Tue, 17 Sep 2019 10:31:45 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20190829213321.4092-4-mike.leach@linaro.org> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190917_023149_018359_E1C88F8E X-CRM114-Status: GOOD ( 17.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gregkh@linuxfoundation.org, corbet@lwn.net Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Mike, On 29/08/2019 22:33, Mike Leach wrote: > TRCACATRn registers have match bits for secure and non-secure exception > levels which are not accessible by the sysfs API. > This adds a new sysfs parameter to enable this - addr_exlevel_s_ns. > Looks good to me. Some minor nits below. > Signed-off-by: Mike Leach > --- > .../coresight/coresight-etm4x-sysfs.c | 42 +++++++++++++++++++ > 1 file changed, 42 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > index cc8156318018..b520f3c1521f 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > @@ -1233,6 +1233,47 @@ static ssize_t addr_context_store(struct device *dev, > } > static DEVICE_ATTR_RW(addr_context); > > +static ssize_t addr_exlevel_s_ns_show(struct device *dev, > + struct device_attribute *attr, > + char *buf) > +{ > + u8 idx; > + unsigned long val; > + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > + struct etmv4_config *config = &drvdata->config; > + > + spin_lock(&drvdata->spinlock); > + idx = config->addr_idx; > + val = BMVAL(config->addr_acc[idx], 14, 8); > + spin_unlock(&drvdata->spinlock); > + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > +} > + > +static ssize_t addr_exlevel_s_ns_store(struct device *dev, > + struct device_attribute *attr, > + const char *buf, size_t size) > +{ > + u8 idx; > + unsigned long val; > + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > + struct etmv4_config *config = &drvdata->config; > + > + if (kstrtoul(buf, 16, &val)) > + return -EINVAL; Can this be 0 instead of 16 to accept any base ? > + > + if (val & ~0x7F) minor nit: Do we need to use (GENMASK(14, 8) >> 8) here instead of hard coding the mask ? > + return -EINVAL; > + > + spin_lock(&drvdata->spinlock); > + idx = config->addr_idx; > + /* clear Exlevel_ns & Exlevel_s bits[14:12, 11:8] */ It may be worth adding a comment that bit[15] is RES0. > + config->addr_acc[idx] &= ~(GENMASK(14, 8)); > + config->addr_acc[idx] |= (val << 8); > + spin_unlock(&drvdata->spinlock); > + return size; > +} > +static DEVICE_ATTR_RW(addr_exlevel_s_ns); > + > static ssize_t seq_idx_show(struct device *dev, > struct device_attribute *attr, > char *buf) > @@ -2038,6 +2079,7 @@ static struct attribute *coresight_etmv4_attrs[] = { > &dev_attr_addr_stop.attr, > &dev_attr_addr_ctxtype.attr, > &dev_attr_addr_context.attr, > + &dev_attr_addr_exlevel_s_ns.attr, > &dev_attr_seq_idx.attr, > &dev_attr_seq_state.attr, > &dev_attr_seq_event.attr, Either ways, irrespective of the above comments : Reviewed-by: Suzuki K Poulose _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel