From: Stephen Boyd <sboyd@kernel.org>
To: conor+dt@kernel.org, heiko@sntech.de, kever.yang@rock-chips.com,
krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com,
robh+dt@kernel.org, zhangqing@rock-chips.com
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org,
linux-kernel@vger.kernel.org, huangtao@rock-chips.com,
andy.yan@rock-chips.com
Subject: Re: [PATCH v4 0/4] rockchip: add GATE_LINK
Date: Mon, 23 Oct 2023 18:47:17 -0700 [thread overview]
Message-ID: <b0af9e04bafb07e8a73e8f242a4ff556.sboyd@kernel.org> (raw)
In-Reply-To: <20231018070144.8512-1-zhangqing@rock-chips.com>
Quoting Elaine Zhang (2023-10-18 00:01:40)
> Recent Rockchip SoCs have a new hardware block called Native Interface
> Unit (NIU), which gates clocks to devices behind them. These effectively
> need two parent clocks.
> Use GATE_LINK to handle this.
Why can't pm clks be used here? The qcom clk driver has been doing that
for some time now.
$ git grep pm_clk_add -- drivers/clk/qcom/
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next prev parent reply other threads:[~2023-10-24 1:48 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-18 7:01 [PATCH v4 0/4] rockchip: add GATE_LINK Elaine Zhang
2023-10-18 7:01 ` [PATCH v4 1/4] clk: gate: export clk_gate_endisable Elaine Zhang
2023-10-18 7:01 ` [PATCH v4 2/4] clk: rockchip: add support for gate link Elaine Zhang
2023-10-18 7:01 ` [PATCH v4 3/4] dt-bindings: clock: rk3588: export PCLK_VO1GRF clk id Elaine Zhang
2023-10-18 7:14 ` Krzysztof Kozlowski
2023-10-18 7:01 ` [PATCH v4 4/4] clk: rockchip: rk3588: Adjust the GATE_LINK parameter Elaine Zhang
2023-10-20 17:42 ` [PATCH v4 0/4] rockchip: add GATE_LINK Sebastian Reichel
2023-10-24 1:47 ` Stephen Boyd [this message]
2023-10-25 19:48 ` Sebastian Reichel
2023-10-25 21:40 ` Stephen Boyd
2023-10-26 2:25 ` zhangqing
2023-10-26 21:29 ` Stephen Boyd
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