[PATCH 0/4] mmc: mtk-sd: improve support for mt7620 variant

[PATCH 0/4] mmc: mtk-sd: improve support for mt7620 variant

[Shiji Yang]

This patchset adds some specific initialization parameters to the
legacy MIPS mt7620 variant to improve the driver stability. These
changes have been tested on MT7620, MT7621 and MT7628. I didn't
notice any negative feedback since it was merged into a popular
Linux distribution OpenWrt. So it's time to upstream it.

Shiji Yang (4):
  mmc: mtk-sd: disable auto CMD23 support for mt7620
  mmc: mtk-sd: add default tuning parameters for mt7620
  mmc: mtk-sd: add default PAD control for mt7620
  mmc: mtk-sd: use default PATCH_BIT register values for mt7620

 drivers/mmc/host/mtk-sd.c | 52 +++++++++++++++++++++++++++++++++++----
 1 file changed, 47 insertions(+), 5 deletions(-)

-- 
2.50.0

[PATCH 1/4] mmc: mtk-sd: disable auto CMD23 support for mt7620

[Shiji Yang]

MT7628 ProgrammingGuide indicates that the host controller version
3.0 and later support auto CMD23 function. However, it doesn't
define the SD command register BIT[29](Auto CMD23 enable bit). I
guess the legacy MIPS MT762x series SoCs don't support this feature
at all. The experiment on JDCloud RE-SP-01B(MT7621 + 128 GiB EMMC)
shows that disabling auto CMD23 can fix the following IO errors:

[  143.344604] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
[  143.353661] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
[  143.362662] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
[  143.371684] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
[  143.380684] I/O error, dev mmcblk0boot0, sector 0 op 0x0:(READ) flags 0x80700 phys_seg 4 prio class 0
[  143.390414] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
[  143.399468] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
[  143.408516] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
[  143.417556] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
[  143.426590] I/O error, dev mmcblk0boot0, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
[  143.435585] Buffer I/O error on dev mmcblk0boot0, logical block 0, async page read

Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
---
 drivers/mmc/host/mtk-sd.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index 31eb90536..53d63bb4e 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -445,6 +445,7 @@ struct mtk_mmc_compatible {
 	u8 pop_en_cnt;
 	bool enhance_rx;
 	bool support_64g;
+	bool support_cmd23;
 	bool use_internal_cd;
 	bool support_new_tx;
 	bool support_new_rx;
@@ -535,6 +536,7 @@ static const struct mtk_mmc_compatible mt2701_compat = {
 	.stop_clk_fix = false,
 	.enhance_rx = false,
 	.support_64g = false,
+	.support_cmd23 = true,
 };
 
 static const struct mtk_mmc_compatible mt2712_compat = {
@@ -549,6 +551,7 @@ static const struct mtk_mmc_compatible mt2712_compat = {
 	.stop_dly_sel = 3,
 	.enhance_rx = true,
 	.support_64g = true,
+	.support_cmd23 = true,
 };
 
 static const struct mtk_mmc_compatible mt6779_compat = {
@@ -563,6 +566,7 @@ static const struct mtk_mmc_compatible mt6779_compat = {
 	.stop_dly_sel = 3,
 	.enhance_rx = true,
 	.support_64g = true,
+	.support_cmd23 = true,
 };
 
 static const struct mtk_mmc_compatible mt6795_compat = {
@@ -576,6 +580,7 @@ static const struct mtk_mmc_compatible mt6795_compat = {
 	.stop_clk_fix = false,
 	.enhance_rx = false,
 	.support_64g = false,
+	.support_cmd23 = true,
 };
 
 static const struct mtk_mmc_compatible mt7620_compat = {
@@ -588,6 +593,7 @@ static const struct mtk_mmc_compatible mt7620_compat = {
 	.busy_check = false,
 	.stop_clk_fix = false,
 	.enhance_rx = false,
+	.support_cmd23 = false,
 	.use_internal_cd = true,
 };
 
@@ -603,6 +609,7 @@ static const struct mtk_mmc_compatible mt7622_compat = {
 	.stop_dly_sel = 3,
 	.enhance_rx = true,
 	.support_64g = false,
+	.support_cmd23 = true,
 };
 
 static const struct mtk_mmc_compatible mt7986_compat = {
@@ -618,6 +625,7 @@ static const struct mtk_mmc_compatible mt7986_compat = {
 	.stop_dly_sel = 3,
 	.enhance_rx = true,
 	.support_64g = true,
+	.support_cmd23 = true,
 };
 
 static const struct mtk_mmc_compatible mt8135_compat = {
@@ -631,6 +639,7 @@ static const struct mtk_mmc_compatible mt8135_compat = {
 	.stop_clk_fix = false,
 	.enhance_rx = false,
 	.support_64g = false,
+	.support_cmd23 = true,
 };
 
 static const struct mtk_mmc_compatible mt8173_compat = {
@@ -644,6 +653,7 @@ static const struct mtk_mmc_compatible mt8173_compat = {
 	.stop_clk_fix = false,
 	.enhance_rx = false,
 	.support_64g = false,
+	.support_cmd23 = true,
 };
 
 static const struct mtk_mmc_compatible mt8183_compat = {
@@ -659,6 +669,7 @@ static const struct mtk_mmc_compatible mt8183_compat = {
 	.stop_dly_sel = 3,
 	.enhance_rx = true,
 	.support_64g = true,
+	.support_cmd23 = true,
 };
 
 static const struct mtk_mmc_compatible mt8516_compat = {
@@ -671,6 +682,7 @@ static const struct mtk_mmc_compatible mt8516_compat = {
 	.busy_check = true,
 	.stop_clk_fix = true,
 	.stop_dly_sel = 3,
+	.support_cmd23 = true,
 };
 
 static const struct mtk_mmc_compatible mt8196_compat = {
@@ -687,6 +699,7 @@ static const struct mtk_mmc_compatible mt8196_compat = {
 	.pop_en_cnt = 2,
 	.enhance_rx = true,
 	.support_64g = true,
+	.support_cmd23 = true,
 	.support_new_tx = true,
 	.support_new_rx = true,
 };
@@ -3054,7 +3067,9 @@ static int msdc_drv_probe(struct platform_device *pdev)
 	if (mmc->caps & MMC_CAP_SDIO_IRQ)
 		mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
 
-	mmc->caps |= MMC_CAP_CMD23;
+	if (host->dev_comp->support_cmd23)
+		mmc->caps |= MMC_CAP_CMD23;
+
 	if (host->cqhci)
 		mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
 	/* MMC core transfer sizes tunable parameters */
-- 
2.50.0

Re: [PATCH 1/4] mmc: mtk-sd: disable auto CMD23 support for mt7620

[AngeloGioacchino Del Regno]

Il 19/06/25 07:35, Shiji Yang ha scritto:
> MT7628 ProgrammingGuide indicates that the host controller version
> 3.0 and later support auto CMD23 function. However, it doesn't
> define the SD command register BIT[29](Auto CMD23 enable bit). I
> guess the legacy MIPS MT762x series SoCs don't support this feature
> at all. The experiment on JDCloud RE-SP-01B(MT7621 + 128 GiB EMMC)
> shows that disabling auto CMD23 can fix the following IO errors:
> 
> [  143.344604] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
> [  143.353661] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
> [  143.362662] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
> [  143.371684] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
> [  143.380684] I/O error, dev mmcblk0boot0, sector 0 op 0x0:(READ) flags 0x80700 phys_seg 4 prio class 0
> [  143.390414] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
> [  143.399468] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
> [  143.408516] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
> [  143.417556] mtk-msdc 1e130000.mmc: msdc_track_cmd_data: cmd=6 arg=03B30101; host->error=0x00000002
> [  143.426590] I/O error, dev mmcblk0boot0, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
> [  143.435585] Buffer I/O error on dev mmcblk0boot0, logical block 0, async page read
> 
> Signed-off-by: Shiji Yang <yangshiji66@outlook.com>

Chaotian, could you please confirm that MT7628 does not support AutoCMD23?

Thanks,
Angelo

[PATCH 2/4] mmc: mtk-sd: add default tuning parameters for mt7620

[Shiji Yang]

The MIPS MT762x SoCs require some specific tuning parameters at
different clock frequencies. These legacy SoCs only support max
48~50 MHz High-Speed SD mode. Therefore, the standard tuning step
is not available. We have to hardcode these tuning parameters to
make them work properly.

Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
---
 drivers/mmc/host/mtk-sd.c | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index 53d63bb4e..52198daef 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -79,6 +79,8 @@
 #define MSDC_PATCH_BIT2  0xb8
 #define MSDC_PAD_TUNE    0xec
 #define MSDC_PAD_TUNE0   0xf0
+#define MSDC_DAT_RDDLY0  0xf0
+#define MSDC_DAT_RDDLY1  0xf4
 #define PAD_DS_TUNE      0x188
 #define PAD_CMD_TUNE     0x18c
 #define EMMC51_CFG0	 0x204
@@ -449,6 +451,7 @@ struct mtk_mmc_compatible {
 	bool use_internal_cd;
 	bool support_new_tx;
 	bool support_new_rx;
+	bool mips_mt762x;
 };
 
 struct msdc_tune_para {
@@ -595,6 +598,7 @@ static const struct mtk_mmc_compatible mt7620_compat = {
 	.enhance_rx = false,
 	.support_cmd23 = false,
 	.use_internal_cd = true,
+	.mips_mt762x = true,
 };
 
 static const struct mtk_mmc_compatible mt7622_compat = {
@@ -1090,7 +1094,12 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
 	 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
 	 * tune result of hs200/200Mhz is not suitable for 50Mhz
 	 */
-	if (mmc->actual_clock <= 52000000) {
+	if (host->dev_comp->mips_mt762x &&
+	    mmc->actual_clock > 25000000) {
+		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
+		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
+		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
+	} else if (mmc->actual_clock <= 52000000) {
 		writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
 		if (host->top_base) {
 			writel(host->def_tune_para.emmc_top_control,
@@ -2028,6 +2037,13 @@ static void msdc_init_hw(struct msdc_host *host)
 				     MSDC_PAD_TUNE_RXDLYSEL);
 	}
 
+	if (host->dev_comp->mips_mt762x) {
+		/* Set default tuning parameters */
+		writel(0x84101010, host->base + tune_reg);
+		writel(0x10101010, host->base + MSDC_DAT_RDDLY0);
+		writel(0x10101010, host->base + MSDC_DAT_RDDLY1);
+	}
+
 	if (mmc->caps2 & MMC_CAP2_NO_SDIO) {
 		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
 		sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
-- 
2.50.0

Re: [PATCH 2/4] mmc: mtk-sd: add default tuning parameters for mt7620

[AngeloGioacchino Del Regno]

Il 19/06/25 07:35, Shiji Yang ha scritto:
> The MIPS MT762x SoCs require some specific tuning parameters at
> different clock frequencies. These legacy SoCs only support max
> 48~50 MHz High-Speed SD mode. Therefore, the standard tuning step
> is not available. We have to hardcode these tuning parameters to
> make them work properly.
> 
> Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
> ---
>   drivers/mmc/host/mtk-sd.c | 18 +++++++++++++++++-
>   1 file changed, 17 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
> index 53d63bb4e..52198daef 100644
> --- a/drivers/mmc/host/mtk-sd.c
> +++ b/drivers/mmc/host/mtk-sd.c
> @@ -79,6 +79,8 @@
>   #define MSDC_PATCH_BIT2  0xb8
>   #define MSDC_PAD_TUNE    0xec
>   #define MSDC_PAD_TUNE0   0xf0
> +#define MSDC_DAT_RDDLY0  0xf0
> +#define MSDC_DAT_RDDLY1  0xf4
>   #define PAD_DS_TUNE      0x188
>   #define PAD_CMD_TUNE     0x18c
>   #define EMMC51_CFG0	 0x204
> @@ -449,6 +451,7 @@ struct mtk_mmc_compatible {
>   	bool use_internal_cd;
>   	bool support_new_tx;
>   	bool support_new_rx;
> +	bool mips_mt762x;
>   };
>   
>   struct msdc_tune_para {
> @@ -595,6 +598,7 @@ static const struct mtk_mmc_compatible mt7620_compat = {
>   	.enhance_rx = false,
>   	.support_cmd23 = false,
>   	.use_internal_cd = true,
> +	.mips_mt762x = true,

No, you can't do that - this needs to be done in a clean manner.

Please map that to something that makes sense, as in, add the register definitions
and add something like...

.tune_para = {
	.tune0_rval = FIELD_PREP_CONST(MSDC_PAD_TUNE_DATWRDLY, 16) |
		      FIELD_PREP_CONST(MSDC_PAD_TUNE_DATRDDLY, 16) |
		      FIELD_PREP_CONST(MSDC_PAD_TUNE_CMDRDLY, 16) |
		      FIELD_PREP_CONST(MSDC_PAD_TUNE_CMDRRDLY, 4) |
		      FIELD_PREP_CONST(MSDC_PAD_TUNE_CLKTDLY, 10),
	.rddly0_rval = etc etc etc :-)
};

...then, check if .tune_para is present: if it is, apply the static settings,
otherwise, don't.

Cheers,
Angelo

>   };
>   
>   static const struct mtk_mmc_compatible mt7622_compat = {
> @@ -1090,7 +1094,12 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
>   	 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
>   	 * tune result of hs200/200Mhz is not suitable for 50Mhz
>   	 */
> -	if (mmc->actual_clock <= 52000000) {
> +	if (host->dev_comp->mips_mt762x &&
> +	    mmc->actual_clock > 25000000) {
> +		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
> +		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
> +		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
> +	} else if (mmc->actual_clock <= 52000000) {
>   		writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
>   		if (host->top_base) {
>   			writel(host->def_tune_para.emmc_top_control,
> @@ -2028,6 +2037,13 @@ static void msdc_init_hw(struct msdc_host *host)
>   				     MSDC_PAD_TUNE_RXDLYSEL);
>   	}
>   
> +	if (host->dev_comp->mips_mt762x) {
> +		/* Set default tuning parameters */
> +		writel(0x84101010, host->base + tune_reg);
> +		writel(0x10101010, host->base + MSDC_DAT_RDDLY0);
> +		writel(0x10101010, host->base + MSDC_DAT_RDDLY1);
> +	}
> +
>   	if (mmc->caps2 & MMC_CAP2_NO_SDIO) {
>   		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
>   		sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);

[PATCH 3/4] mmc: mtk-sd: add default PAD control for mt7620

[Shiji Yang]

According to the vendor SDK driver, these legacy MIPS MT762x SoCs
require configuring the IO pin drive strength via the PAD control
registers. This should help improve the stability of electrical
signal transmission.

Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
---
 drivers/mmc/host/mtk-sd.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index 52198daef..276d4e324 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -77,6 +77,9 @@
 #define MSDC_PATCH_BIT   0xb0
 #define MSDC_PATCH_BIT1  0xb4
 #define MSDC_PATCH_BIT2  0xb8
+#define MSDC_PAD_CTRL0   0xe0
+#define MSDC_PAD_CTRL1   0xe4
+#define MSDC_PAD_CTRL2   0xe8
 #define MSDC_PAD_TUNE    0xec
 #define MSDC_PAD_TUNE0   0xf0
 #define MSDC_DAT_RDDLY0  0xf0
@@ -2038,6 +2041,11 @@ static void msdc_init_hw(struct msdc_host *host)
 	}
 
 	if (host->dev_comp->mips_mt762x) {
+		/* Set default pins drive strength */
+		writel(0x000d0044, host->base + MSDC_PAD_CTRL0);
+		writel(0x000e0044, host->base + MSDC_PAD_CTRL1);
+		writel(0x000e0044, host->base + MSDC_PAD_CTRL2);
+
 		/* Set default tuning parameters */
 		writel(0x84101010, host->base + tune_reg);
 		writel(0x10101010, host->base + MSDC_DAT_RDDLY0);
-- 
2.50.0

[PATCH 4/4] mmc: mtk-sd: use default PATCH_BIT register values for mt7620

[Shiji Yang]

The register map definitions of these PATCH_BIT registers seem to be
slightly different from other variants. Use their default values to
respect the vendor SDK driver behaviors.

Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
---
 drivers/mmc/host/mtk-sd.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index 276d4e324..8933cd089 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -1939,7 +1939,8 @@ static void msdc_init_hw(struct msdc_host *host)
 	val |= FIELD_PREP(MSDC_CKGEN_MSDC_DLY_SEL, 1);
 
 	/* First MSDC_PATCH_BIT setup is done: pull the trigger! */
-	writel(val, host->base + MSDC_PATCH_BIT);
+	if (!host->dev_comp->mips_mt762x)
+		writel(val, host->base + MSDC_PATCH_BIT);
 
 	/* Set wr data, crc status, cmd response turnaround period for UHS104 */
 	pb1_val = FIELD_PREP(MSDC_PB1_WRDAT_CRC_TACNTR, 1);
@@ -2002,8 +2003,10 @@ static void msdc_init_hw(struct msdc_host *host)
 		pb2_val |= MSDC_PB2_SUPPORT_64G;
 
 	/* Patch Bit 1/2 setup is done: pull the trigger! */
-	writel(pb1_val, host->base + MSDC_PATCH_BIT1);
-	writel(pb2_val, host->base + MSDC_PATCH_BIT2);
+	if (!host->dev_comp->mips_mt762x) {
+		writel(pb1_val, host->base + MSDC_PATCH_BIT1);
+		writel(pb2_val, host->base + MSDC_PATCH_BIT2);
+	}
 	sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
 
 	if (host->dev_comp->data_tune) {
-- 
2.50.0

Re: [PATCH 4/4] mmc: mtk-sd: use default PATCH_BIT register values for mt7620

[AngeloGioacchino Del Regno]

Il 19/06/25 07:35, Shiji Yang ha scritto:
> The register map definitions of these PATCH_BIT registers seem to be
> slightly different from other variants. Use their default values to
> respect the vendor SDK driver behaviors.
> 

Just read the values that do work from the registers on your board and on
the downstream kernel, after which, map the resulting value to the patch
bits that you can find here in this driver.

If there's any difference, add the relevant definitions.

Cheers,
Angelo

> Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
> ---
>   drivers/mmc/host/mtk-sd.c | 9 ++++++---
>   1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
> index 276d4e324..8933cd089 100644
> --- a/drivers/mmc/host/mtk-sd.c
> +++ b/drivers/mmc/host/mtk-sd.c
> @@ -1939,7 +1939,8 @@ static void msdc_init_hw(struct msdc_host *host)
>   	val |= FIELD_PREP(MSDC_CKGEN_MSDC_DLY_SEL, 1);
>   
>   	/* First MSDC_PATCH_BIT setup is done: pull the trigger! */
> -	writel(val, host->base + MSDC_PATCH_BIT);
> +	if (!host->dev_comp->mips_mt762x)
> +		writel(val, host->base + MSDC_PATCH_BIT);
>   
>   	/* Set wr data, crc status, cmd response turnaround period for UHS104 */
>   	pb1_val = FIELD_PREP(MSDC_PB1_WRDAT_CRC_TACNTR, 1);
> @@ -2002,8 +2003,10 @@ static void msdc_init_hw(struct msdc_host *host)
>   		pb2_val |= MSDC_PB2_SUPPORT_64G;
>   
>   	/* Patch Bit 1/2 setup is done: pull the trigger! */
> -	writel(pb1_val, host->base + MSDC_PATCH_BIT1);
> -	writel(pb2_val, host->base + MSDC_PATCH_BIT2);
> +	if (!host->dev_comp->mips_mt762x) {
> +		writel(pb1_val, host->base + MSDC_PATCH_BIT1);
> +		writel(pb2_val, host->base + MSDC_PATCH_BIT2);
> +	}
>   	sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
>   
>   	if (host->dev_comp->data_tune) {