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Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kFSbo-0002w6-E9; Tue, 08 Sep 2020 01:39:44 +0000 Received: from szxga07-in.huawei.com ([45.249.212.35] helo=huawei.com) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kFSbk-0002uQ-Kj for linux-arm-kernel@lists.infradead.org; Tue, 08 Sep 2020 01:39:42 +0000 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 5052EF00016F6E5E0383; Tue, 8 Sep 2020 09:39:27 +0800 (CST) Received: from [10.67.76.227] (10.67.76.227) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.487.0; Tue, 8 Sep 2020 09:39:21 +0800 Subject: Re: [PATCH] coresight: etm4x: fix issues on trcseqevr access To: Mike Leach , Mathieu Poirier References: <1599043033-57852-1-git-send-email-jonathan.zhouwen@huawei.com> <20200903174245.GC312784@xps15> From: Jonathan Zhou Message-ID: Date: Tue, 8 Sep 2020 09:39:21 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.2.1 MIME-Version: 1.0 In-Reply-To: Content-Language: en-GB X-Originating-IP: [10.67.76.227] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200907_213941_442172_CDEDBE7A X-CRM114-Status: GOOD ( 22.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Shaokun Zhang , lizixian@hisilicon.com, linux-arm-kernel , Suzuki K Poulose Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Mike, On 08/09/2020 00:51, Mike Leach wrote: > Hi, > > On Thu, 3 Sep 2020 at 18:42, Mathieu Poirier wrote: >> >> On Wed, Sep 02, 2020 at 06:37:13PM +0800, Jonathan Zhou wrote: >>> The TRCSEQEVR(3) is reserved, using '@nrseqstate - 1' instead to avoid >>> accessing the reserved register. >>> >>> Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU low power states") >>> Cc: Mathieu Poirier >>> Cc: Suzuki K Poulose >>> Cc: Mike Leach >>> Cc: Shaokun Zhang >>> Cc: lizixian@hisilicon.com >>> >>> Signed-off-by: Jonathan Zhou >>> --- >>> drivers/hwtracing/coresight/coresight-etm4x.c | 4 ++-- >>> 1 file changed, 2 insertions(+), 2 deletions(-) >>> >>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c >>> index 96425e818fc2..44e44c817bf8 100644 >>> --- a/drivers/hwtracing/coresight/coresight-etm4x.c >>> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c >>> @@ -1183,7 +1183,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) >>> state->trcvdsacctlr = readl(drvdata->base + TRCVDSACCTLR); >>> state->trcvdarcctlr = readl(drvdata->base + TRCVDARCCTLR); >>> >>> - for (i = 0; i < drvdata->nrseqstate; i++) >>> + for (i = 0; i < drvdata->nrseqstate - 1; i++) >>> state->trcseqevr[i] = readl(drvdata->base + TRCSEQEVRn(i)); >> >> The section 3.4.3 "Guidelines for trace unit registers to be saved and restored" >> of the ETM4 Architecture Specification (ARM IHI0064F ID042818) is clear on the >> fact that registers TRCSEQEVR0-3 have to be taken into account when saving the > > I think this is a typo in the TRM. I'll ping the docs people in ARM. > >> trace unit state. >> > > Looking @ the register descriptions for TRCSEQEVRn (7.3.63) in the > above document n=0-2. > The number of states is set by TRCIDR5.NUMSEQSTATE (7.3.35). This can > take the value 0 or 4. > If 4 then there are 3 TRCSEQEVR(n) registers - 0 to 2 - one for each > state transition. > > Thus this patch is correct in using nrseqstate - 1. > Thanks for point out this, I just never thought it may be a typo. Regards Jonathan > Regards > > Mike > >> Thanks, >> Mathieu >> >>> >>> state->trcseqrstevr = readl(drvdata->base + TRCSEQRSTEVR); >>> @@ -1288,7 +1288,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) >>> writel_relaxed(state->trcvdsacctlr, drvdata->base + TRCVDSACCTLR); >>> writel_relaxed(state->trcvdarcctlr, drvdata->base + TRCVDARCCTLR); >>> >>> - for (i = 0; i < drvdata->nrseqstate; i++) >>> + for (i = 0; i < drvdata->nrseqstate - 1; i++) >>> writel_relaxed(state->trcseqevr[i], >>> drvdata->base + TRCSEQEVRn(i)); >>> -- >>> 1.9.1 >>> > > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel