From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7247DC00448 for ; Thu, 25 Aug 2022 03:14:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:CC:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=xy1iWvuTqfTE6KZLGibf0+dodJr2z045b7GvdTjCa8g=; b=aeSK80DFpmmmac PFm97Dm1FDPFEjhlOKwc51BxaMBNFvoVa2g+cOafUDAreywzRhXw/qhcv062y11dTj0lPHTHTVD8P xaHZf6jqteabwI3JFZk/hIyAJ1Ilg9Gsp+WuHU1iZB8vsV/tX/yaLUOGsdY7o5vrRGoG/Iu5aWdx6 Vm8++rlXHIVHXbRUVzQqUL4Bi4zTtwAE0tOfGA1/nqgZfkk3SomuCeGnkGpYrYBdTwGoHmkWIct2n jrPtGEH++0VpbnAfw22nRbED5IeTCIunYNVytBun+fxkq/mXQ0sIGZgnGOyZyAohpJPu/M8IvqijV be1sAvv5z0QRZF0xfP0g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oR3Ix-0051aD-JC; Thu, 25 Aug 2022 03:13:15 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oR3It-0051VK-KD; Thu, 25 Aug 2022 03:13:13 +0000 X-UUID: f712166734484b469680037ba77eed0c-20220824 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=fMaxPbtRsPB7u5/xEhCvW3M/iJpDMnXyBFXjy70UF8Q=; b=IhzdWue/0SaNx/dDDyF05TtNQ8j4ueePxvnpqkCUjTGT6TJwtLuQ2UJdD6onRiG63wI07U63znB9eLpvd0U1YvKcZfq9lmOzF1pMOyVy+xE7Pg1fvt4gstjQcBLlKPwSBY3UZlCyBeum0X+xNCLBSEztN2gacPcOMEX6xXwLpiw=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.10,REQID:e81b3117-5fd9-424f-8d40-1b07096c9ee7,OB:0,L OB:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_ Ham,ACTION:release,TS:0 X-CID-META: VersionHash:84eae18,CLOUDID:d2727f55-e800-47dc-8adf-0c936acf4f1b,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:11|1,File: nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: f712166734484b469680037ba77eed0c-20220824 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 510533725; Wed, 24 Aug 2022 20:10:37 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Thu, 25 Aug 2022 10:19:58 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 25 Aug 2022 10:19:58 +0800 Message-ID: Subject: Re: [PATCH v26 07/10] soc: mediatek: mmsys: add mmsys for support 64 reset bits From: Nancy.Lin To: Matthias Brugger , Rob Herring , Chun-Kuang Hu , "Philipp Zabel" , , "AngeloGioacchino Del Regno" , , CC: David Airlie , Daniel Vetter , "Nathan Chancellor" , Nick Desaulniers , "jason-jh . lin" , Yongqiang Niu , , , , , , , , Date: Thu, 25 Aug 2022 10:19:58 +0800 In-Reply-To: References: <20220819061011.7672-1-nancy.lin@mediatek.com> <20220819061011.7672-8-nancy.lin@mediatek.com> <44c86ad9-8158-0a8a-ce31-a995c8d10e0b@gmail.com> <140b3cd10317a5db781df180ce4efb697cdd641b.camel@mediatek.com> <7c59d86501c39fa6e0e182f4a537de814320426e.camel@mediatek.com> X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220824_201311_719585_B23E2A16 X-CRM114-Status: GOOD ( 54.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Matthias, Thanks for your comment. On Wed, 2022-08-24 at 13:41 +0200, Matthias Brugger wrote: > > On 24/08/2022 04:44, Nancy.Lin wrote: > > Hi Matthias, > > > > Thanks for your comment. > > > > On Tue, 2022-08-23 at 14:08 +0200, Matthias Brugger wrote: > > > > > > On 23/08/2022 13:30, Nancy.Lin wrote: > > > > Hi Matthias, > > > > > > > > Thanks for the review. > > > > > > > > On Tue, 2022-08-23 at 12:20 +0200, Matthias Brugger wrote: > > > > > > > > > > On 19/08/2022 08:10, Nancy.Lin wrote: > > > > > > Add mmsys for support 64 reset bits. It is a preparation > > > > > > for > > > > > > MT8195 > > > > > > vdosys1 HW reset. MT8195 vdosys1 has more than 32 reset > > > > > > bits. > > > > > > > > > > > > 1. Add the number of reset bits in mmsys private data > > > > > > 2. move the whole "reset register code section" behind the > > > > > > "get mmsys->data" code section for getting the num_resets > > > > > > in > > > > > > mmsys- > > > > > > > data. > > > > > > > > > > > > Signed-off-by: Nancy.Lin > > > > > > Reviewed-by: AngeloGioacchino Del Regno < > > > > > > angelogioacchino.delregno@collabora.com> > > > > > > Reviewed-by: CK Hu > > > > > > Tested-by: Bo-Chen Chen > > > > > > --- > > > > > > drivers/soc/mediatek/mtk-mmsys.c | 40 > > > > > > +++++++++++++++++++++- > > > > > > --- > > > > > > ------- > > > > > > drivers/soc/mediatek/mtk-mmsys.h | 1 + > > > > > > 2 files changed, 27 insertions(+), 14 deletions(-) > > > > > > > > > > > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c > > > > > > b/drivers/soc/mediatek/mtk-mmsys.c > > > > > > index 999be064103b..20ae751ad8a7 100644 > > > > > > --- a/drivers/soc/mediatek/mtk-mmsys.c > > > > > > +++ b/drivers/soc/mediatek/mtk-mmsys.c > > > > > > @@ -20,6 +20,8 @@ > > > > > > #include "mt8195-mmsys.h" > > > > > > #include "mt8365-mmsys.h" > > > > > > > > > > > > +#define MMSYS_SW_RESET_PER_REG 32 > > > > > > + > > > > > > static const struct mtk_mmsys_driver_data > > > > > > mt2701_mmsys_driver_data = { > > > > > > .clk_driver = "clk-mt2701-mm", > > > > > > .routes = mmsys_default_routing_table, > > > > > > @@ -86,6 +88,7 @@ static const struct mtk_mmsys_driver_data > > > > > > mt8173_mmsys_driver_data = { > > > > > > .routes = mmsys_default_routing_table, > > > > > > .num_routes = > > > > > > ARRAY_SIZE(mmsys_default_routing_table), > > > > > > .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, > > > > > > + .num_resets = 32, > > > > > > }; > > > > > > > > > > > > static const struct mtk_mmsys_match_data > > > > > > mt8173_mmsys_match_data > > > > > > = { > > > > > > @@ -100,6 +103,7 @@ static const struct > > > > > > mtk_mmsys_driver_data > > > > > > mt8183_mmsys_driver_data = { > > > > > > .routes = mmsys_mt8183_routing_table, > > > > > > .num_routes = > > > > > > ARRAY_SIZE(mmsys_mt8183_routing_table), > > > > > > .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, > > > > > > + .num_resets = 32, > > > > > > }; > > > > > > > > > > > > static const struct mtk_mmsys_match_data > > > > > > mt8183_mmsys_match_data > > > > > > = { > > > > > > @@ -114,6 +118,7 @@ static const struct > > > > > > mtk_mmsys_driver_data > > > > > > mt8186_mmsys_driver_data = { > > > > > > .routes = mmsys_mt8186_routing_table, > > > > > > .num_routes = > > > > > > ARRAY_SIZE(mmsys_mt8186_routing_table), > > > > > > .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, > > > > > > + .num_resets = 32, > > > > > > }; > > > > > > > > > > > > static const struct mtk_mmsys_match_data > > > > > > mt8186_mmsys_match_data > > > > > > = { > > > > > > @@ -128,6 +133,7 @@ static const struct > > > > > > mtk_mmsys_driver_data > > > > > > mt8192_mmsys_driver_data = { > > > > > > .routes = mmsys_mt8192_routing_table, > > > > > > .num_routes = > > > > > > ARRAY_SIZE(mmsys_mt8192_routing_table), > > > > > > .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, > > > > > > + .num_resets = 32, > > > > > > > > > > You didn't reply to Nicolas regarding the reset numbers. I > > > > > actually > > > > > agree with > > > > > him that we will need the num_resets declared for all > > > > > devices. > > > > > Why do > > > > > you think > > > > > this is not the case? > > > > > > > > > > Regards, > > > > > Matthias > > > > > > > > > > > > > Sorry, I lost Nicolas's email. > > > > > > > > I checked with the mmsys git log with reset controller > > > > function. > > > > > > > > 1. Enric add mmsys reset controller function in [1]/[2]. > > > > => in mtk_mmsys_reset_update(), all mmsys reset offset is > > > > MMSYS_SW0_RST_B (0x140). > > > > > > > > 2. After Enric's patch, Rex add sw0_rst_offset in mmsys driver > > > > data > > > > in > > > > [3]. > > > > > > > > So, I think sw0_rst_offset is not zero. Instead of only add > > > > num_resets > > > > but also need to add sw0_rst_offset for all mmsys. What do you > > > > think ? > > > > > > > > > > Good point. It seems we have a bug in the driver. Either all SoCs > > > have the > > > reset, but it's broken since > > > 62dc30150c06 ("soc: mediatek: mmsys: add sw0_rst_offset in mmsys > > > driver data") > > > or we are adding a reset controller independently if the silicon > > > has > > > one, which > > > would be an error in: > > > f27ef2856343 ("soc: mediatek: mmsys: Add reset controller > > > support") > > > > > > We have to find that out. > > > > > > Regards, > > > Matthias > > > > > > In [2], I think the first revision of Enric's reset controller is > > added > > for 8173 and 8183, not for all mmsys device. > > =>[v3,4/7] arm64: dts: mt8173: Add the mmsys reset bit to > > reset the > > dsi0 > > =>[v3,5/7] arm64: dts: mt8183: Add the mmsys reset bit to > > reset the > > dsi0 > > > > In [3], Rex only add sw0_rst_offset in 8173 and 8183 mmsys driver > > data. > > > > > > > For other SoCs, like mt2701,mt2712..., these SoCs even don't define > > mmsys hw reset bit[4]. So I think only set the num_resets to 32 or > > 64 > > to those mmsys devices who really need the reset control, others > > set to > > 0(same as my v26 patch). > > > > Thanks for looking into this, please see my comment further below. > > > > > > [4]mt2701-resets.h > > https://urldefense.com/v3/__https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/dt-bindings/reset/mt2701-resets.h?id=62dc30150c06774a8122c52aedd0eddaceaf5940__;!!CTRNKA9wMg0ARbw!3j1YotescyEb7vq_dITIlc-FdtaFSslPkcn3B-Sw95Zf613Z-TPG4FK0BdCyW0Fb$ > > > > > > Regards, > > Nancy > > > > > > > > [1] > > > > > > > > https://urldefense.com/v3/__https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/soc/mediatek/mtk-mmsys.c?id=f27ef2856343e2ddc392975d7b15120442e4d7b7__;!!CTRNKA9wMg0ARbw!3cWAYlD1mrWRmNZy0zoJs8MNiD3s7K9PteJI9cGEvu_qp3VShfqxsBTb_fKynszs$ > > > > > > > > [2] > > > > > > > > > > > > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/cover/20210825102632.601614-1-enric.balletbo@collabora.com/__;!!CTRNKA9wMg0ARbw!3cWAYlD1mrWRmNZy0zoJs8MNiD3s7K9PteJI9cGEvu_qp3VShfqxsBTb_cH-3nM8$ > > > > > > > > [3] > > > > > > > > > > > > https://urldefense.com/v3/__https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/soc/mediatek/mtk-mmsys.c?id=62dc30150c06774a8122c52aedd0eddaceaf5940__;!!CTRNKA9wMg0ARbw!3cWAYlD1mrWRmNZy0zoJs8MNiD3s7K9PteJI9cGEvu_qp3VShfqxsBTb_VXEsbNa$ > > > > > > > > > > > > Regards, > > > > Nancy > > > > > > > > > > > }; > > > > > > > > > > > > static const struct mtk_mmsys_match_data > > > > > > mt8192_mmsys_match_data > > > > > > = { > > > > > > @@ -288,13 +294,19 @@ static int > > > > > > mtk_mmsys_reset_update(struct > > > > > > reset_controller_dev *rcdev, unsigned l > > > > > > { > > > > > > struct mtk_mmsys *mmsys = container_of(rcdev, > > > > > > struct > > > > > > mtk_mmsys, > > > > > > rcdev); > > > > > > unsigned long flags; > > > > > > + u32 offset; > > > > > > + u32 reg; > > > > > > + > > > > > > + offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32); > > > > > > + id = id % MMSYS_SW_RESET_PER_REG; > > > > > > + reg = mmsys->data->sw0_rst_offset + offset; > > > > > > > > > > > > spin_lock_irqsave(&mmsys->lock, flags); > > > > > > > > > > > > if (assert) > > > > > > - mtk_mmsys_update_bits(mmsys, mmsys->data- > > > > > > > sw0_rst_offset, BIT(id), 0, NULL); > > > > > > > > > > > > + mtk_mmsys_update_bits(mmsys, reg, BIT(id), 0, > > > > > > NULL); > > > > > > else > > > > > > - mtk_mmsys_update_bits(mmsys, mmsys->data- > > > > > > > sw0_rst_offset, BIT(id), BIT(id), NULL); > > > > > > > > > > > > + mtk_mmsys_update_bits(mmsys, reg, BIT(id), > > > > > > BIT(id), > > > > > > NULL); > > > > > > > > > > > > spin_unlock_irqrestore(&mmsys->lock, flags); > > > > > > > > > > > > @@ -351,18 +363,6 @@ static int mtk_mmsys_probe(struct > > > > > > platform_device *pdev) > > > > > > return ret; > > > > > > } > > > > > > > > > > > > - spin_lock_init(&mmsys->lock); > > > > > > - > > > > > > - mmsys->rcdev.owner = THIS_MODULE; > > > > > > - mmsys->rcdev.nr_resets = 32; > > > > > > - mmsys->rcdev.ops = &mtk_mmsys_reset_ops; > > > > > > - mmsys->rcdev.of_node = pdev->dev.of_node; > > > > > > - ret = devm_reset_controller_register(&pdev->dev, > > > > > > &mmsys- > > > > > > > rcdev); > > > > > > > > > > > > - if (ret) { > > > > > > - dev_err(&pdev->dev, "Couldn't register mmsys > > > > > > reset > > > > > > controller: %d\n", ret); > > > > > > - return ret; > > > > > > - } > > > > > > - > > > > > > res = platform_get_resource(pdev, > > > > > > IORESOURCE_MEM, 0); > > > > > > if (!res) { > > > > > > dev_err(dev, "Couldn't get mmsys > > > > > > resource\n"); > > > > > > @@ -384,6 +384,18 @@ static int mtk_mmsys_probe(struct > > > > > > platform_device *pdev) > > > > > > mmsys->data = match_data->drv_data[0]; > > > > > > } > > > > > > > > > > > > + spin_lock_init(&mmsys->lock); > > > > > > + > > > > > > + mmsys->rcdev.owner = THIS_MODULE; > > > > > > + mmsys->rcdev.nr_resets = mmsys->data->num_resets; > > > > > > + mmsys->rcdev.ops = &mtk_mmsys_reset_ops; > > > > > > + mmsys->rcdev.of_node = pdev->dev.of_node; > > > > > > + ret = devm_reset_controller_register(&pdev->dev, > > > > > > &mmsys- > > > > > > > rcdev); > > > > > > > > > > > > + if (ret) { > > > > > > + dev_err(&pdev->dev, "Couldn't register mmsys > > > > > > reset > > > > > > controller: %d\n", ret); > > > > > > + return ret; > > > > > > + } > > > > > > + > > > This code is only relevant if mmsys->data->num_resets > 0. Let's > check for that > before setting up and registering an interrupt controller. What do > you think? > > Regards, > Matthias > There is no doubt that we need to check num_resets > 0 before registering reset controller. I will add it in the next revision. Regards, Nancy > > > > > > #if IS_REACHABLE(CONFIG_MTK_CMDQ) > > > > > > ret = cmdq_dev_get_client_reg(dev, &mmsys- > > > > > > >cmdq_base, > > > > > > 0); > > > > > > if (ret) > > > > > > diff --git a/drivers/soc/mediatek/mtk-mmsys.h > > > > > > b/drivers/soc/mediatek/mtk-mmsys.h > > > > > > index f01ba206481d..20a271b80b3b 100644 > > > > > > --- a/drivers/soc/mediatek/mtk-mmsys.h > > > > > > +++ b/drivers/soc/mediatek/mtk-mmsys.h > > > > > > @@ -92,6 +92,7 @@ struct mtk_mmsys_driver_data { > > > > > > const struct mtk_mmsys_routes *routes; > > > > > > const unsigned int num_routes; > > > > > > const u16 sw0_rst_offset; > > > > > > + const u32 num_resets; > > > > > > }; > > > > > > > > > > > > struct mtk_mmsys_match_data { > > > > > > > > > > > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel