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From: Manikanta Maddireddy <mmaddireddy@nvidia.com>
To: "Niklas Cassel" <cassel@kernel.org>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Heiko Stuebner" <heiko@sntech.de>
Cc: Koichiro Den <den@valinux.co.jp>,
	Damien Le Moal <dlemoal@kernel.org>,
	linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org
Subject: Re: [PATCH 3/9] PCI: dw-rockchip: Describe RK3588 BAR4 DMA ctrl window
Date: Mon, 23 Feb 2026 09:40:17 +0530	[thread overview]
Message-ID: <b1978807-df13-48a9-a99e-30b2a8e459be@nvidia.com> (raw)
In-Reply-To: <20260217212707.2450423-14-cassel@kernel.org>


On 18/02/26 2:57 am, Niklas Cassel wrote:
> From: Koichiro Den <den@valinux.co.jp>
>
> On RK3588 PCIe3_4L in EP mode, the integrated DMA controller registers
> are permanently mapped to BAR4 and must not be repurposed by EPF
> drivers.
>
> When the remote peer needs to access these registers, it must use the
> fixed BAR4 window instead of creating another inbound mapping in a
> different BAR. Mixing the fixed window with an additional mapping can
> lead to incorrect behavior.
>
> Advertise the DMA controller MMIO window as a reserved BAR subregion so
> EPF drivers can reuse it safely.
>
> Signed-off-by: Koichiro Den <den@valinux.co.jp>
> Signed-off-by: Niklas Cassel <cassel@kernel.org>
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
I have not verified this on rk3588, therefore I am not adding "Tested 
by" tag
> ---
>   drivers/pci/controller/dwc/pcie-dw-rockchip.c | 15 ++++++++++++++-
>   1 file changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> index 5b17da63151d..ecc28093c589 100644
> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> @@ -403,6 +403,15 @@ static const struct pci_epc_features rockchip_pcie_epc_features_rk3568 = {
>   	.bar[BAR_5] = { .type = BAR_RESIZABLE, },
>   };
>   
> +static const struct pci_epc_bar_rsvd_region rk3588_bar4_rsvd[] = {
> +	{
> +		/* DMA_CAP (BAR4: DMA Port Logic Structure) */
> +		.type = PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO,
> +		.offset = 0x0,
> +		.size = 0x2000,
> +	},
> +};
> +
>   /*
>    * BAR4 on rk3588 exposes the ATU Port Logic Structure to the host regardless of
>    * iATU settings for BAR4. This means that BAR4 cannot be used by an EPF driver,
> @@ -420,7 +429,11 @@ static const struct pci_epc_features rockchip_pcie_epc_features_rk3588 = {
>   	.bar[BAR_1] = { .type = BAR_RESIZABLE, },
>   	.bar[BAR_2] = { .type = BAR_RESIZABLE, },
>   	.bar[BAR_3] = { .type = BAR_RESIZABLE, },
> -	.bar[BAR_4] = { .type = BAR_RESERVED, },
> +	.bar[BAR_4] = {
> +		.type = BAR_RESERVED,
> +		.nr_rsvd_regions = ARRAY_SIZE(rk3588_bar4_rsvd),
> +		.rsvd_regions = rk3588_bar4_rsvd,
> +	},
>   	.bar[BAR_5] = { .type = BAR_RESIZABLE, },
>   };
>   


  reply	other threads:[~2026-02-23  4:10 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20260217212707.2450423-11-cassel@kernel.org>
2026-02-17 21:27 ` [PATCH 1/9] PCI: endpoint: Introduce pci_epc_bar_type BAR_64BIT_UPPER Niklas Cassel
2026-02-17 21:57   ` Frank Li
     [not found]     ` <81af7f88-b9c1-457f-9a21-a7b15a13d374@nvidia.com>
2026-02-23 10:14       ` Geert Uytterhoeven
2026-02-24 13:54         ` Manikanta Maddireddy
2026-02-17 21:27 ` [PATCH 3/9] PCI: dw-rockchip: Describe RK3588 BAR4 DMA ctrl window Niklas Cassel
2026-02-23  4:10   ` Manikanta Maddireddy [this message]
2026-02-17 21:27 ` [PATCH 5/9] PCI: dwc: Replace BAR_RESERVED with BAR_DISABLED in glue drivers Niklas Cassel
2026-02-17 22:15   ` Frank Li
2026-02-23  4:46     ` Manikanta Maddireddy
2026-02-25 14:56       ` Niklas Cassel
2026-02-17 21:27 ` [PATCH 6/9] PCI: dwc: Disable BARs in common code instead of in each glue driver Niklas Cassel
2026-02-17 23:00   ` Frank Li

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