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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-MBO-RS-ID: 95a871c755375494b81 X-MBO-RS-META: gsb99t9ej18ugjwbxn3iuk755yh9d7m3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260908_092730_455682_3ED7E65C X-CRM114-Status: GOOD ( 15.82 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 9/8/26 10:46 AM, Geert Uytterhoeven wrote: Hello Geert, > As I am not PCIe DT expert, I am comparing this to the corresponding > patch for R-Car V4H, which I have already queued as commit > 7fe73a3a3f2c3718 ("arm64: dts: renesas: r8a779g0: Add GICv3 ITS and > update PCIe nodes") in renesas-devel, but which probably needs some > updates. I sent a fix for that one: [PATCH] arm64: dts: renesas: r8a779g0: Add MSI cells to GICv3 ITS >> --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi >> +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi >> @@ -691,6 +691,8 @@ pciec0: pcie@e65d0000 { >> resets = <&cpg 624>, <&cpg 1121>; >> reset-names = "pwr", "core"; >> max-link-speed = <4>; >> + msi-parent = <&its 0>; > > This has an extra cell "0", which is probably correct, given > "#msi-cells = <1>" below. > >> + msi-map = <0x0 &its 0x0 0x10000>; > > This is not present on R-Car V4H (which is probably wrong). > > Interestingly, Documentation/devicetree/bindings/pci/pci-ep.yaml > documents msi-map for endpoint node, so should it be added to the > pcie-ep node, too? I do not think we should be adding it until we can test ITS with EP ? This patch adds the ITS only to the RC side, where I can test it.