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Tue, 11 Feb 2020 11:54:20 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 81911100050; Tue, 11 Feb 2020 11:54:18 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag5node3.st.com [10.75.127.15]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 72A2F2AEAAB; Tue, 11 Feb 2020 11:54:18 +0100 (CET) Received: from [10.48.0.71] (10.75.127.44) by SFHDAG5NODE3.st.com (10.75.127.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 11 Feb 2020 11:54:17 +0100 Subject: Re: [PATCH v2] counter: stm32-timer-cnt: add power management support To: William Breathitt Gray References: <1581355198-30428-1-git-send-email-fabrice.gasnier@st.com> <20200210174550.GA4626@icarus> From: Fabrice Gasnier Message-ID: Date: Tue, 11 Feb 2020 11:54:17 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <20200210174550.GA4626@icarus> Content-Language: en-US X-Originating-IP: [10.75.127.44] X-ClientProxiedBy: SFHDAG4NODE2.st.com (10.75.127.11) To SFHDAG5NODE3.st.com (10.75.127.15) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-02-11_03:2020-02-10, 2020-02-11 signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200211_025426_761843_F0606B98 X-CRM114-Status: GOOD ( 20.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alexandre.torgue@st.com, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mcoquelin.stm32@gmail.com, linux-stm32@st-md-mailman.stormreply.com, jic23@kernel.org, benjamin.gaignard@st.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2/10/20 6:45 PM, William Breathitt Gray wrote: > On Mon, Feb 10, 2020 at 06:19:58PM +0100, Fabrice Gasnier wrote: >> Add suspend/resume PM sleep ops. When going to low power, enforce the >> counter isn't active. Gracefully restore its state upon resume in case >> it's been left enabled prior to suspend. >> >> Acked-by: William Breathitt Gray >> Signed-off-by: Fabrice Gasnier >> --- >> Changes in v2: >> - Don't refuse to suspend in case the counter has been left enabled. >> Gracefully disable it and restore its state upon resume. >> --- >> drivers/counter/stm32-timer-cnt.c | 63 +++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 63 insertions(+) >> >> diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c >> index 3eafcce..50496f4 100644 >> --- a/drivers/counter/stm32-timer-cnt.c >> +++ b/drivers/counter/stm32-timer-cnt.c >> @@ -12,6 +12,7 @@ >> #include > > Unrelated to your patch but it caught my eye: are iio headers necessary > for this file? I suspect they are not needed since this driver does not > make use of the IIO interface. Hi William, Yes, you're right. Thanks for pointing this! I'll push a patch on top of this one to fix it. BTW, I'm not sure if this needs to be a marked as a fix, as this seems a quite minor issue? Best Regards, Fabrice > > William Breathitt Gray > >> #include >> #include >> +#include >> #include >> >> #define TIM_CCMR_CCXS (BIT(8) | BIT(0)) >> @@ -20,11 +21,20 @@ >> #define TIM_CCER_MASK (TIM_CCER_CC1P | TIM_CCER_CC1NP | \ >> TIM_CCER_CC2P | TIM_CCER_CC2NP) >> >> +struct stm32_timer_regs { >> + u32 cr1; >> + u32 cnt; >> + u32 smcr; >> + u32 arr; >> +}; >> + >> struct stm32_timer_cnt { >> struct counter_device counter; >> struct regmap *regmap; >> struct clk *clk; >> u32 ceiling; >> + bool enabled; >> + struct stm32_timer_regs bak; >> }; >> >> /** >> @@ -224,6 +234,9 @@ static ssize_t stm32_count_enable_write(struct counter_device *counter, >> clk_disable(priv->clk); >> } >> >> + /* Keep enabled state to properly handle low power states */ >> + priv->enabled = enable; >> + >> return len; >> } >> >> @@ -358,10 +371,59 @@ static int stm32_timer_cnt_probe(struct platform_device *pdev) >> priv->counter.num_signals = ARRAY_SIZE(stm32_signals); >> priv->counter.priv = priv; >> >> + platform_set_drvdata(pdev, priv); >> + >> /* Register Counter device */ >> return devm_counter_register(dev, &priv->counter); >> } >> >> +static int __maybe_unused stm32_timer_cnt_suspend(struct device *dev) >> +{ >> + struct stm32_timer_cnt *priv = dev_get_drvdata(dev); >> + >> + /* Only take care of enabled counter: don't disturb other MFD child */ >> + if (priv->enabled) { >> + /* Backup registers that may get lost in low power mode */ >> + regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr); >> + regmap_read(priv->regmap, TIM_ARR, &priv->bak.arr); >> + regmap_read(priv->regmap, TIM_CNT, &priv->bak.cnt); >> + regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1); >> + >> + /* Disable the counter */ >> + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); >> + clk_disable(priv->clk); >> + } >> + >> + return pinctrl_pm_select_sleep_state(dev); >> +} >> + >> +static int __maybe_unused stm32_timer_cnt_resume(struct device *dev) >> +{ >> + struct stm32_timer_cnt *priv = dev_get_drvdata(dev); >> + int ret; >> + >> + ret = pinctrl_pm_select_default_state(dev); >> + if (ret) >> + return ret; >> + >> + if (priv->enabled) { >> + clk_enable(priv->clk); >> + >> + /* Restore registers that may have been lost */ >> + regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr); >> + regmap_write(priv->regmap, TIM_ARR, priv->bak.arr); >> + regmap_write(priv->regmap, TIM_CNT, priv->bak.cnt); >> + >> + /* Also re-enables the counter */ >> + regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1); >> + } >> + >> + return 0; >> +} >> + >> +static SIMPLE_DEV_PM_OPS(stm32_timer_cnt_pm_ops, stm32_timer_cnt_suspend, >> + stm32_timer_cnt_resume); >> + >> static const struct of_device_id stm32_timer_cnt_of_match[] = { >> { .compatible = "st,stm32-timer-counter", }, >> {}, >> @@ -373,6 +435,7 @@ static struct platform_driver stm32_timer_cnt_driver = { >> .driver = { >> .name = "stm32-timer-counter", >> .of_match_table = stm32_timer_cnt_of_match, >> + .pm = &stm32_timer_cnt_pm_ops, >> }, >> }; >> module_platform_driver(stm32_timer_cnt_driver); >> -- >> 2.7.4 >> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel