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Sat, 19 Nov 2022 12:32:04 +0000 MIME-Version: 1.0 Date: Sat, 19 Nov 2022 12:32:04 +0000 From: Marc Zyngier To: Reiji Watanabe Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvmarm@lists.linux.dev, kvm@vger.kernel.org, James Morse , Suzuki K Poulose , Alexandru Elisei , Oliver Upton , Ricardo Koller Subject: Re: [PATCH v4 09/16] KVM: arm64: PMU: Do not let AArch32 change the counters' top 32 bits In-Reply-To: References: <20221113163832.3154370-1-maz@kernel.org> <20221113163832.3154370-10-maz@kernel.org> User-Agent: Roundcube Webmail/1.4.13 Message-ID: X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: reijiw@google.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvmarm@lists.linux.dev, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, alexandru.elisei@arm.com, oliver.upton@linux.dev, ricarkol@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221119_043212_937291_4798C682 X-CRM114-Status: GOOD ( 20.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2022-11-18 07:45, Reiji Watanabe wrote: > Hi Marc, > > On Sun, Nov 13, 2022 at 8:38 AM Marc Zyngier wrote: >> >> Even when using PMUv3p5 (which implies 64bit counters), there is >> no way for AArch32 to write to the top 32 bits of the counters. >> The only way to influence these bits (other than by counting >> events) is by writing PMCR.P==1. >> >> Make sure we obey the architecture and preserve the top 32 bits >> on a counter update. >> >> Signed-off-by: Marc Zyngier >> --- >> arch/arm64/kvm/pmu-emul.c | 35 +++++++++++++++++++++++++++-------- >> 1 file changed, 27 insertions(+), 8 deletions(-) >> >> diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c >> index ea0c8411641f..419e5e0a13d0 100644 >> --- a/arch/arm64/kvm/pmu-emul.c >> +++ b/arch/arm64/kvm/pmu-emul.c >> @@ -119,13 +119,8 @@ u64 kvm_pmu_get_counter_value(struct kvm_vcpu >> *vcpu, u64 select_idx) >> return counter; >> } >> >> -/** >> - * kvm_pmu_set_counter_value - set PMU counter value >> - * @vcpu: The vcpu pointer >> - * @select_idx: The counter index >> - * @val: The counter value >> - */ >> -void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, >> u64 val) >> +static void kvm_pmu_set_counter(struct kvm_vcpu *vcpu, u64 >> select_idx, u64 val, >> + bool force) >> { >> u64 reg; >> >> @@ -135,12 +130,36 @@ void kvm_pmu_set_counter_value(struct kvm_vcpu >> *vcpu, u64 select_idx, u64 val) >> kvm_pmu_release_perf_event(&vcpu->arch.pmu.pmc[select_idx]); >> >> reg = counter_index_to_reg(select_idx); >> + >> + if (vcpu_mode_is_32bit(vcpu) && select_idx != >> ARMV8_PMU_CYCLE_IDX && >> + !force) { >> + /* >> + * Even with PMUv3p5, AArch32 cannot write to the top >> + * 32bit of the counters. The only possible course of >> + * action is to use PMCR.P, which will reset them to >> + * 0 (the only use of the 'force' parameter). >> + */ >> + val = lower_32_bits(val); >> + val |= upper_32_bits(__vcpu_sys_reg(vcpu, reg)); > > Shouldn't the result of upper_32_bits() be shifted 32bits left > before ORing (to maintain the upper 32bits of the current value) ? Indeed, and it only shows that AArch32 has had no testing whatsoever :-(. I'll fix it up locally. Thanks again, M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel