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From: Reinette Chatre <reinette.chatre@intel.com>
To: Ben Horgan <ben.horgan@arm.com>
Cc: <amitsinght@marvell.com>, <baisheng.gao@unisoc.com>,
	<baolin.wang@linux.alibaba.com>, <carl@os.amperecomputing.com>,
	<dave.martin@arm.com>, <david@kernel.org>,
	<dfustini@baylibre.com>, <fenghuay@nvidia.com>,
	<gshan@redhat.com>, <james.morse@arm.com>, <jic23@kernel.org>,
	<kobak@nvidia.com>, <lcherian@marvell.com>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <peternewman@google.com>,
	<punit.agrawal@oss.qualcomm.com>, <quic_jiles@quicinc.com>,
	<rohit.mathew@arm.com>, <scott@os.amperecomputing.com>,
	<sdonthineni@nvidia.com>, <tan.shaopeng@fujitsu.com>,
	<xhao@linux.alibaba.com>, <zengheng4@huawei.com>,
	<x86@kernel.org>
Subject: Re: [PATCH v4 5/5] arm64: mpam: Add memory bandwidth usage (MBWU) documentation
Date: Thu, 2 Jul 2026 07:46:46 -0700	[thread overview]
Message-ID: <b2dae9c4-d0b3-4ec2-884a-569020039b5f@intel.com> (raw)
In-Reply-To: <0ebb1365-9883-4974-9e8f-05c2eaa01fb1@arm.com>

Hi Ben,

On 7/2/26 2:20 AM, Ben Horgan wrote:
> On 7/1/26 23:38, Reinette Chatre wrote:
>> On 5/20/26 2:24 PM, Ben Horgan wrote:

...

>>> --- a/Documentation/arch/arm64/mpam.rst
>>> +++ b/Documentation/arch/arm64/mpam.rst
>>> @@ -65,6 +65,23 @@ The supported features are:
>>>    there is at least one CSU monitor on each MSC that makes up the L3 group.
>>>    Exposing CSU counters from other caches or devices is not supported.
>>>  
>>> +* Memory Bandwidth Usage (MBWU) on or after the L3 cache.  resctrl uses the
>>> +  L3 cache-id to identify where the memory bandwidth is measured. For this
>>> +  reason the platform must have an L3 cache with cache-id's supplied by
>>> +  firmware. (It doesn't need to support MPAM.)
>>> +
>>> +  Memory bandwidth monitoring makes use of MBWU monitors in each MSC that
>>> +  makes up the L3 group. If the memory bandwidth monitoring is on the memory
>>> +  rather than the L3 then there must be a single global L3 as otherwise it
>>> +  is unknown which L3 the traffic came from.
>>> +
>>> +  To expose 'mbm_total_bytes', the topology of the group of MSC chosen must
>>> +  match the topology of the L3 cache so that the cache-id's can be
>>> +  repainted. For example: Platforms with Memory bandwidth monitors on
>>> +  CPU-less NUMA nodes cannot expose 'mbm_total_bytes' as these nodes do not
>>> +  have a corresponding L3 cache. 'mbm_local_bytes' is not exposed as MPAM
>>> +  cannot distinguish local traffic from global traffic.
>>
>> Hopefully we can get to a point where memory bandwidth monitoring data from
>> CPU-less NUMA nodes can be exposed via resctrl. When considering such possible
> 
> Thank you for your interest here. I hope so too.
> 
>> future I think it may make this work easier to build on if the documentation
>> focuses on what the current implementation supports and leave room for
>> future enhancements by not constraining user space expectation with an absolute
>> like "CPU-less NUMA nodes cannot expose 'mbm_total_bytes'".
> 
> The intention was to describe the current limitations but I do see how
> this can come across as fundamental problems rather than just that we
> need to do some more work to establish how this can be done and
> implement it.
> 
> How about if I add this paragraph at the end?
> 
> All these restrictions based on L3 cache are due to resctrl, currently,
> only supporting monitoring at the scope of the L3 scope. It is expected

How about "at L3 scope" instead of "at the scope of the L3 scope"?

> that going forward more MBWU monitors can be exposed to the user after
> support for more monitoring scopes is added to resctrl.
Looks good to me, thank you.

Reinette


  reply	other threads:[~2026-07-02 14:48 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-20 21:24 [PATCH v4 0/5] arm_mpam: resctrl: Counter Assignment (ABMC) Ben Horgan
2026-05-20 21:24 ` [PATCH v4 1/5] arm_mpam: resctrl: Pick classes for use as MBM counters Ben Horgan
2026-07-02 16:30   ` Fenghua Yu
2026-05-20 21:24 ` [PATCH v4 2/5] arm_mpam: resctrl: Pre-allocate assignable monitors Ben Horgan
2026-05-26  2:50   ` Koba Ko
2026-05-26  8:47     ` Ben Horgan
2026-05-20 21:24 ` [PATCH v4 3/5] arm_mpam: resctrl: Add resctrl_arch_config_cntr() for ABMC use Ben Horgan
2026-05-20 21:24 ` [PATCH v4 4/5] arm_mpam: resctrl: Add resctrl_arch_cntr_read() & resctrl_arch_reset_cntr() Ben Horgan
2026-05-20 21:24 ` [PATCH v4 5/5] arm64: mpam: Add memory bandwidth usage (MBWU) documentation Ben Horgan
2026-07-01 22:38   ` Reinette Chatre
2026-07-02  9:20     ` Ben Horgan
2026-07-02 14:46       ` Reinette Chatre [this message]
2026-07-02 14:58         ` Ben Horgan
2026-07-02 15:46           ` Fenghua Yu
2026-05-27  0:42 ` [PATCH v4 0/5] arm_mpam: resctrl: Counter Assignment (ABMC) Shaopeng Tan (Fujitsu)
2026-05-27 14:36   ` Ben Horgan

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