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Wed, 27 May 2020 05:49:35 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 27 May 2020 05:49:35 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 27 May 2020 05:49:35 -0500 Received: from [10.250.233.85] (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 04RAnV0o056154; Wed, 27 May 2020 05:49:32 -0500 Subject: Re: [PATCH v5 03/14] PCI: cadence: Convert all r/w accessors to perform only 32-bit accesses To: Rob Herring References: <20200522033631.32574-1-kishon@ti.com> <20200522033631.32574-4-kishon@ti.com> From: Kishon Vijay Abraham I Message-ID: Date: Wed, 27 May 2020 16:19:31 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200527_034949_801619_311A63ED X-CRM114-Status: GOOD ( 18.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Lorenzo Pieralisi , Arnd Bergmann , PCI , "linux-kernel@vger.kernel.org" , Tom Joseph , Greg Kroah-Hartman , Bjorn Helgaas , linux-omap , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Rob, On 5/26/2020 8:42 PM, Rob Herring wrote: > On Sun, May 24, 2020 at 9:30 PM Kishon Vijay Abraham I wrote: >> >> Hi Rob, >> >> On 5/22/2020 9:24 PM, Rob Herring wrote: >>> On Thu, May 21, 2020 at 9:37 PM Kishon Vijay Abraham I wrote: >>>> >>>> Certain platforms like TI's J721E using Cadence PCIe IP can perform only >>>> 32-bit accesses for reading or writing to Cadence registers. Convert all >>>> read and write accesses to 32-bit in Cadence PCIe driver in preparation >>>> for adding PCIe support in TI's J721E SoC. >>> >>> Looking more closely I don't think cdns_pcie_ep_assert_intx is okay >>> with this and never can be given the PCI_COMMAND and PCI_STATUS >>> registers are in the same word (IIRC, that's the main reason 32-bit >>> config space accesses are broken). So this isn't going to work at >> >> right, PCI_STATUS has write '1' to clear bits and there's a chance that it >> could be reset while raising legacy interrupt. While this cannot be avoided for >> TI's J721E, other platforms doesn't have to have this limitation. >>> least for EP accesses. And maybe you need a custom .raise_irq() hook >>> to minimize any problems (such as making the RMW atomic at least from >>> the endpoint's perspective). >> >> This is to make sure EP doesn't update in-consistent state when RC is updating >> the PCI_STATUS register? Since this involves two different systems, how do we >> make this atomic? > > You can't make it atomic WRT both systems, but is there locking around > each RMW? Specifically, are preemption and interrupts disabled to > ensure time between a read and write are minimized? You wouldn't want > interrupts disabled during the delay too though (i.e. around > .raise_irq()). Okay, I'll add spin spin_lock_irqsave() in cdns_pcie_write_sz(). As you also pointed below that delay for legacy interrupt is wrong and it has to be fixed (with a later series). How do you want to handle cdns_pcie_ep_fn_writew() now? Because now we are changing the default implementation to perform only 32-bit access (used for legacy interrupt, msi-x interrupt and while writing standard headers) and it's not okay only for legacy interrupts for platforms other than TI. So just for legacy interrupt, you want me to add a different accessor which does not perform 32-bit writes (while we add a different .raise_irq for TI platform? > > BTW, I've asked this question before, but aren't PCI legacy interrupts > level triggered? If so, isn't generating a pulse wrong? You are right. This is wrong and it has to be fixed. I'll work on this later. Thanks Kishon _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel