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[72.137.118.218]) by smtp.gmail.com with ESMTPSA id r8-20020ae9d608000000b0074856680834sm4077578qkk.132.2023.03.29.14.35.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Mar 2023 14:35:16 -0700 (PDT) Message-ID: Subject: Re: [RFC PATCH] arch_topology: Pre-allocate cacheinfo from primary CPU From: Radu Rendec To: Pierre Gondois , Sudeep Holla Cc: linux-arm-kernel@lists.infradead.org, Adrien Thierry , Eric Chanudet Date: Wed, 29 Mar 2023 17:35:15 -0400 In-Reply-To: References: <20230323224242.31142-1-rrendec@redhat.com> <428070eb-d1d0-cd04-53c7-91e13ab64867@arm.com> <20230329150308.aaajdsh74olpjach@bogus> User-Agent: Evolution 3.46.4 (3.46.4-1.fc37) MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230329_143523_764133_AA9D02CF X-CRM114-Status: GOOD ( 19.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 2023-03-29 at 17:39 +0200, Pierre Gondois wrote: > On 3/29/23 17:03, Sudeep Holla wrote: > > On Wed, Mar 29, 2023 at 04:42:07PM +0200, Pierre Gondois wrote: > > > > > > This would mean that for all architectures, the cacheinfo would come from > > > ACPI/DT first..... > > > > x86 doesn't fall into the above category. So we need to ensure it continues > > to work with no errors. > > Ok, then maybe having a second arch specific function like > init_cache_level() would work. > > This function would be called in fetch_cache_info() after > init_of_cache_level()/acpi_get_cache_info() fail. It would fetch > cache info anywhere but in DT/ACPI. > Archs that don't want it would not implement it, and it would > allow the others to get the num_leaves/levels during early boot. Hello Pierre, If I understand correctly, in the case of arm64 this new function would use CLIDR_EL1 to detect the number of leaves/levels, right? But since init_cpu_topology() calls fetch_cache_info() for each CPU, doesn't this mean we would end up doing CLIDR_EL1 based detection for the secondary CPUs by running the (arch specific) detection code on the primary CPU? My intimate knowledge of arm64 is very limited, but I *assumed* one of the reasons why detect_cache_attributes() (and init_cache_level()) run on the secondary CPU today is because not all CPUs are necessarily identical. Another possible reason I can think of is because maybe on some architectures auto-detection isn't possible altogether before the secondary CPU is brought up. In particular, for arm64 is it possible that CLIDR_EL1 may not look the same depending on the CPU that reads it? What about SoC's with asymmetrical CPU cores? (no concrete example here, just assuming this is a real/possible thing) Best regards, Radu _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel