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Thu, 19 Sep 2019 15:54:52 +0000 From: To: , , , , , Subject: Re: [PATCH 17/23] mtd: spi-nor: Fix clearing of QE bit on lock()/unlock() Thread-Topic: [PATCH 17/23] mtd: spi-nor: Fix clearing of QE bit on lock()/unlock() Thread-Index: AQHVbXBXffWwZrBoIkKrGGyrhA4/GaczE40AgAAWrYA= Date: Thu, 19 Sep 2019 15:54:52 +0000 Message-ID: References: <20190917155426.7432-1-tudor.ambarus@microchip.com> <20190917155426.7432-18-tudor.ambarus@microchip.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR0601CA0032.eurprd06.prod.outlook.com (2603:10a6:800:1e::42) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [86.120.240.252] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: d864dd75-6ef7-43f1-b1eb-08d73d19b529 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(5600167)(711020)(4605104)(1401327)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020); 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 09/19/2019 05:33 PM, Vignesh Raghavendra wrote: > Hi Tudor > Hi, Vignesh, > [...] > > On 17-Sep-19 9:25 PM, Tudor.Ambarus@microchip.com wrote: >> +static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 status_new, >> + u8 mask) >> +{ >> + int ret; >> + u8 *sr_cr = nor->bouncebuf; >> + u8 cr_written; >> + >> + /* Make sure we don't overwrite the contents of Status Register 2. */ >> + if (!(nor->flags & SNOR_F_NO_READ_CR)) { > Assuming SNOR_F_NO_READ_CR is not set... > when SNOR_F_NO_READ_CR is not set, I read the Status Register 2 on the next line: >> + ret = spi_nor_read_cr(nor, &sr_cr[1]); >> + if (ret) >> + return ret; >> + } else if (nor->flash.quad_enable) { >> + /* >> + * If the Status Register 2 Read command (35h) is not >> + * supported, we should at least be sure we don't >> + * change the value of the SR2 Quad Enable bit. >> + * >> + * We can safely assume that when the Quad Enable method is >> + * set, the value of the QE bit is one, as a consequence of the >> + * nor->flash.quad_enable() call. >> + * >> + * We can safely assume that the Quad Enable bit is present in >> + * the Status Register 2 at BIT(1). According to the JESD216 >> + * revB standard, BFPT DWORDS[15], bits 22:20, the 16-bit >> + * Write Status (01h) command is available just for the cases >> + * in which the QE bit is described in SR2 at BIT(1). >> + */ when SNOR_F_NO_READ_CR is set and nor->flash.quad_enable != NULL, Status Register 2 (CR) is equal to CR_QUAD_EN_SPAN. >> + sr_cr[1] = CR_QUAD_EN_SPAN; >> + } else { if SNOR_F_NO_READ_CR is set and nor->flash.quad_enable == NULL we don't need to enable Quad Mode, so Status Register 2 is 0. >> + sr_cr[1] = 0; >> + } >> + > CR_QUAD_EN_SPAN will not be in sr_cr[1] when we reach here. So code > won't enable quad mode. > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel