[PATCH 0/5] Use mmio-sram driver for Keystone MSMC RAM

[PATCH 0/5] Use mmio-sram driver for Keystone MSMC RAM

[Suman Anna]

Hi,

The Keystone 2 family of SoCs have an on-chip RAM called the
Multicore Shared Memory (MSM) RAM. This RAM is accessible through
the Multicore Shared Memory Controller (MSMC). This series represents
these on-chip RAMs as sram nodes so that the memory allocations
can be managed by the in-kernel mmio-sram driver.

The first 4 patches adds the basic SRAM nodes on each of the SoCs,
and the last patch enables the generic on-chip SRAM driver for
keystone defconfig.

regards
Suman


Suman Anna (5):
  ARM: dts: keystone-k2hk: Add MSM RAM node
  ARM: dts: keystone-k2l: Add MSM RAM node
  ARM: dts: keystone-k2e: Add MSM RAM node
  ARM: dts: keystone-k2g: Add MSM RAM node
  ARM: configs: keystone: Enable Generic on-chip SRAM driver

 arch/arm/boot/dts/keystone-k2e.dtsi  | 8 ++++++++
 arch/arm/boot/dts/keystone-k2g.dtsi  | 8 ++++++++
 arch/arm/boot/dts/keystone-k2hk.dtsi | 8 ++++++++
 arch/arm/boot/dts/keystone-k2l.dtsi  | 8 ++++++++
 arch/arm/configs/keystone_defconfig  | 1 +
 5 files changed, 33 insertions(+)

-- 
2.9.3

[PATCH 1/5] ARM: dts: keystone-k2hk: Add MSM RAM node

[Suman Anna]

Add the RAM managed by the Multicore Shared Memory Controller (MSMC)
as a mmio-sram node. The Keystone 2 Hawking SoC has 6 MB of such
memory. Any specific MSM memory range needed by a software module
ought to be reserved using an appropriate child node.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm/boot/dts/keystone-k2hk.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/keystone-k2hk.dtsi b/arch/arm/boot/dts/keystone-k2hk.dtsi
index 8f67fa8df936..39e88d815235 100644
--- a/arch/arm/boot/dts/keystone-k2hk.dtsi
+++ b/arch/arm/boot/dts/keystone-k2hk.dtsi
@@ -46,6 +46,14 @@
 	soc {
 		/include/ "keystone-k2hk-clocks.dtsi"
 
+		msm_ram: msmram at 0c000000 {
+			compatible = "mmio-sram";
+			reg = <0x0c000000 0x600000>;
+			ranges = <0x0 0x0c000000 0x600000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
 		dspgpio0: keystone_dsp_gpio at 02620240 {
 			compatible = "ti,keystone-dsp-gpio";
 			gpio-controller;
-- 
2.9.3

[PATCH 2/5] ARM: dts: keystone-k2l: Add MSM RAM node

[Suman Anna]

Add the RAM managed by the Multicore Shared Memory Controller (MSMC)
as a mmio-sram node. The Keystone 2 Lamarr SoC has 2 MB of such
memory. Any specific MSM memory range needed by a software module
ought to be reserved using an appropriate child node.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm/boot/dts/keystone-k2l.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/keystone-k2l.dtsi b/arch/arm/boot/dts/keystone-k2l.dtsi
index 2ee3d0ac2816..b2994c9ded43 100644
--- a/arch/arm/boot/dts/keystone-k2l.dtsi
+++ b/arch/arm/boot/dts/keystone-k2l.dtsi
@@ -34,6 +34,14 @@
 	soc {
 		/include/ "keystone-k2l-clocks.dtsi"
 
+		msm_ram: msmram at 0c000000 {
+			compatible = "mmio-sram";
+			reg = <0x0c000000 0x200000>;
+			ranges = <0x0 0x0c000000 0x200000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
 		uart2: serial at 02348400 {
 			compatible = "ns16550a";
 			current-speed = <115200>;
-- 
2.9.3

[PATCH 3/5] ARM: dts: keystone-k2e: Add MSM RAM node

[Suman Anna]

Add the RAM managed by the Multicire Shared Memory Controller (MSMC)
as a mmio-sram node. The Keystone 2 Edison SoC has 2 MB of such
memory. Any specific MSM memory range needed by a software module
ought to be reserved using an appropriate child node.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm/boot/dts/keystone-k2e.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/keystone-k2e.dtsi b/arch/arm/boot/dts/keystone-k2e.dtsi
index 9a51b8c88581..48846c36cbed 100644
--- a/arch/arm/boot/dts/keystone-k2e.dtsi
+++ b/arch/arm/boot/dts/keystone-k2e.dtsi
@@ -46,6 +46,14 @@
 	soc {
 		/include/ "keystone-k2e-clocks.dtsi"
 
+		msm_ram: msmram at 0c000000 {
+			compatible = "mmio-sram";
+			reg = <0x0c000000 0x200000>;
+			ranges = <0x0 0x0c000000 0x200000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
 		usb: usb at 2680000 {
 			interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
 			dwc3 at 2690000 {
-- 
2.9.3

[PATCH 4/5] ARM: dts: keystone-k2g: Add MSM RAM node

[Suman Anna]

Add the RAM managed by the Multicore Shared Memory Controller (MSMC)
as a mmio-sram node. The Keystone 2 K2G SoC has 1 MB of such memory.
Any specific MSM memory range needed by a software module ought to
be reserved using an appropriate child node.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm/boot/dts/keystone-k2g.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi
index 3372615b885c..be1db22db0d3 100644
--- a/arch/arm/boot/dts/keystone-k2g.dtsi
+++ b/arch/arm/boot/dts/keystone-k2g.dtsi
@@ -76,6 +76,14 @@
 		ranges = <0x0 0x0 0x0 0xc0000000>;
 		dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>;
 
+		msm_ram: msmram at 0c000000 {
+			compatible = "mmio-sram";
+			reg = <0x0c000000 0x100000>;
+			ranges = <0x0 0x0c000000 0x100000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
 		k2g_pinctrl: pinmux at 02621000 {
 			compatible = "pinctrl-single";
 			reg = <0x02621000 0x410>;
-- 
2.9.3

[PATCH 5/5] ARM: configs: keystone: Enable Generic on-chip SRAM driver

[Suman Anna]

All the Keystone 2 SoCs have an on-chip RAM called the MultiCore
Shared Memory (MSM) RAM managed by the Multicore Shared Memory
Controller (MSMC) that provides faster access compared to normal
DDR.

This patch enables the Generic on-chip SRAM driver that manages
this memory in software.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm/configs/keystone_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig
index 71b42e66488a..28afcf7733f2 100644
--- a/arch/arm/configs/keystone_defconfig
+++ b/arch/arm/configs/keystone_defconfig
@@ -126,6 +126,7 @@ CONFIG_MTD_NAND_DAVINCI=y
 CONFIG_MTD_SPI_NOR=y
 CONFIG_MTD_UBI=y
 CONFIG_BLK_DEV_LOOP=y
+CONFIG_SRAM=y
 CONFIG_EEPROM_AT24=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
-- 
2.9.3

[PATCH 0/5] Use mmio-sram driver for Keystone MSMC RAM

[Santosh Shilimkar]

Hi Suman,

On 9/1/2016 3:58 PM, Suman Anna wrote:
> Hi,
>
> The Keystone 2 family of SoCs have an on-chip RAM called the
> Multicore Shared Memory (MSM) RAM. This RAM is accessible through
> the Multicore Shared Memory Controller (MSMC). This series represents
> these on-chip RAMs as sram nodes so that the memory allocations
> can be managed by the in-kernel mmio-sram driver.
>
> The first 4 patches adds the basic SRAM nodes on each of the SoCs,
> and the last patch enables the generic on-chip SRAM driver for
> keystone defconfig.
>
The series looks good in general but I would like to understand
the users of this memory in kernel. Is that going to be posted
as a follow up patch ? Is the Power controller going to make
use of this SRAM for PM code ?

Regards,
Santosh

[PATCH 0/5] Use mmio-sram driver for Keystone MSMC RAM

[Suman Anna]

Hi Santosh,

On 09/07/2016 11:11 AM, Santosh Shilimkar wrote:
> Hi Suman,
> 
> On 9/1/2016 3:58 PM, Suman Anna wrote:
>> Hi,
>>
>> The Keystone 2 family of SoCs have an on-chip RAM called the
>> Multicore Shared Memory (MSM) RAM. This RAM is accessible through
>> the Multicore Shared Memory Controller (MSMC). This series represents
>> these on-chip RAMs as sram nodes so that the memory allocations
>> can be managed by the in-kernel mmio-sram driver.
>>
>> The first 4 patches adds the basic SRAM nodes on each of the SoCs,
>> and the last patch enables the generic on-chip SRAM driver for
>> keystone defconfig.
>>
> The series looks good in general but I would like to understand
> the users of this memory in kernel. Is that going to be posted
> as a follow up patch ? Is the Power controller going to make
> use of this SRAM for PM code ?

Yes, the users will eventually follow. Power Controller code is not
gonna be using this SRAM, it has its own RAM. This memory is gonna be
split between various functional features like IPC, OPTEE integration,
we already have the Boot Monitor code using this. We will have the
memory split by either having static child nodes or drivers requesting
the memory using gen_pool API.

regards
Suman

[PATCH 0/5] Use mmio-sram driver for Keystone MSMC RAM

[Santosh Shilimkar]

On 9/7/2016 9:22 AM, Suman Anna wrote:
> Hi Santosh,
>
> On 09/07/2016 11:11 AM, Santosh Shilimkar wrote:
>> Hi Suman,
>>
>> On 9/1/2016 3:58 PM, Suman Anna wrote:
>>> Hi,
>>>
>>> The Keystone 2 family of SoCs have an on-chip RAM called the
>>> Multicore Shared Memory (MSM) RAM. This RAM is accessible through
>>> the Multicore Shared Memory Controller (MSMC). This series represents
>>> these on-chip RAMs as sram nodes so that the memory allocations
>>> can be managed by the in-kernel mmio-sram driver.
>>>
>>> The first 4 patches adds the basic SRAM nodes on each of the SoCs,
>>> and the last patch enables the generic on-chip SRAM driver for
>>> keystone defconfig.
>>>
>> The series looks good in general but I would like to understand
>> the users of this memory in kernel. Is that going to be posted
>> as a follow up patch ? Is the Power controller going to make
>> use of this SRAM for PM code ?
>
> Yes, the users will eventually follow. Power Controller code is not
> gonna be using this SRAM, it has its own RAM. This memory is gonna be
> split between various functional features like IPC, OPTEE integration,
> we already have the Boot Monitor code using this. We will have the
> memory split by either having static child nodes or drivers requesting
> the memory using gen_pool API.
>
OK. Its good to add the code at least with one active user of it.
Since this has to anyway wait for another merge window, please post the
users of it so that I can pull the combined patchset.

Regards,
Santosh

[PATCH 0/5] Use mmio-sram driver for Keystone MSMC RAM

[Suman Anna]

On 09/07/2016 11:25 AM, Santosh Shilimkar wrote:
> On 9/7/2016 9:22 AM, Suman Anna wrote:
>> Hi Santosh,
>>
>> On 09/07/2016 11:11 AM, Santosh Shilimkar wrote:
>>> Hi Suman,
>>>
>>> On 9/1/2016 3:58 PM, Suman Anna wrote:
>>>> Hi,
>>>>
>>>> The Keystone 2 family of SoCs have an on-chip RAM called the
>>>> Multicore Shared Memory (MSM) RAM. This RAM is accessible through
>>>> the Multicore Shared Memory Controller (MSMC). This series represents
>>>> these on-chip RAMs as sram nodes so that the memory allocations
>>>> can be managed by the in-kernel mmio-sram driver.
>>>>
>>>> The first 4 patches adds the basic SRAM nodes on each of the SoCs,
>>>> and the last patch enables the generic on-chip SRAM driver for
>>>> keystone defconfig.
>>>>
>>> The series looks good in general but I would like to understand
>>> the users of this memory in kernel. Is that going to be posted
>>> as a follow up patch ? Is the Power controller going to make
>>> use of this SRAM for PM code ?
>>
>> Yes, the users will eventually follow. Power Controller code is not
>> gonna be using this SRAM, it has its own RAM. This memory is gonna be
>> split between various functional features like IPC, OPTEE integration,
>> we already have the Boot Monitor code using this. We will have the
>> memory split by either having static child nodes or drivers requesting
>> the memory using gen_pool API.
>>
> OK. Its good to add the code at least with one active user of it.
> Since this has to anyway wait for another merge window, please post the
> users of it so that I can pull the combined patchset.

Yeah, will do. The first user will mostly be the corresponding child
nodes for the boot monitor.

regards
Suman

[PATCH 0/5] Use mmio-sram driver for Keystone MSMC RAM

[santosh.shilimkar at oracle.com]

Hi Suman,

On 9/7/16 9:25 AM, Santosh Shilimkar wrote:
> On 9/7/2016 9:22 AM, Suman Anna wrote:
>> Hi Santosh,
>>
>> On 09/07/2016 11:11 AM, Santosh Shilimkar wrote:
>>> Hi Suman,
>>>
>>> On 9/1/2016 3:58 PM, Suman Anna wrote:
>>>> Hi,
>>>>
>>>> The Keystone 2 family of SoCs have an on-chip RAM called the
>>>> Multicore Shared Memory (MSM) RAM. This RAM is accessible through
>>>> the Multicore Shared Memory Controller (MSMC). This series represents
>>>> these on-chip RAMs as sram nodes so that the memory allocations
>>>> can be managed by the in-kernel mmio-sram driver.
>>>>
>>>> The first 4 patches adds the basic SRAM nodes on each of the SoCs,
>>>> and the last patch enables the generic on-chip SRAM driver for
>>>> keystone defconfig.
>>>>
>>> The series looks good in general but I would like to understand
>>> the users of this memory in kernel. Is that going to be posted
>>> as a follow up patch ? Is the Power controller going to make
>>> use of this SRAM for PM code ?
>>
>> Yes, the users will eventually follow. Power Controller code is not
>> gonna be using this SRAM, it has its own RAM. This memory is gonna be
>> split between various functional features like IPC, OPTEE integration,
>> we already have the Boot Monitor code using this. We will have the
>> memory split by either having static child nodes or drivers requesting
>> the memory using gen_pool API.
>>
> OK. Its good to add the code at least with one active user of it.
> Since this has to anyway wait for another merge window, please post the
> users of it so that I can pull the combined patchset.
>
Are you going to post new patchset or you dropped this series ?

If you want me to include it for next merge window, please post
refreshed patchset.

Regards,
Santosh

[PATCH 0/5] Use mmio-sram driver for Keystone MSMC RAM

[Suman Anna]

Hi Santosh,

> 
> On 9/7/16 9:25 AM, Santosh Shilimkar wrote:
>> On 9/7/2016 9:22 AM, Suman Anna wrote:
>>> Hi Santosh,
>>>
>>> On 09/07/2016 11:11 AM, Santosh Shilimkar wrote:
>>>> Hi Suman,
>>>>
>>>> On 9/1/2016 3:58 PM, Suman Anna wrote:
>>>>> Hi,
>>>>>
>>>>> The Keystone 2 family of SoCs have an on-chip RAM called the
>>>>> Multicore Shared Memory (MSM) RAM. This RAM is accessible through
>>>>> the Multicore Shared Memory Controller (MSMC). This series represents
>>>>> these on-chip RAMs as sram nodes so that the memory allocations
>>>>> can be managed by the in-kernel mmio-sram driver.
>>>>>
>>>>> The first 4 patches adds the basic SRAM nodes on each of the SoCs,
>>>>> and the last patch enables the generic on-chip SRAM driver for
>>>>> keystone defconfig.
>>>>>
>>>> The series looks good in general but I would like to understand
>>>> the users of this memory in kernel. Is that going to be posted
>>>> as a follow up patch ? Is the Power controller going to make
>>>> use of this SRAM for PM code ?
>>>
>>> Yes, the users will eventually follow. Power Controller code is not
>>> gonna be using this SRAM, it has its own RAM. This memory is gonna be
>>> split between various functional features like IPC, OPTEE integration,
>>> we already have the Boot Monitor code using this. We will have the
>>> memory split by either having static child nodes or drivers requesting
>>> the memory using gen_pool API.
>>>
>> OK. Its good to add the code at least with one active user of it.
>> Since this has to anyway wait for another merge window, please post the
>> users of it so that I can pull the combined patchset.
>>
> Are you going to post new patchset or you dropped this series ?
> 
> If you want me to include it for next merge window, please post
> refreshed patchset.

No, haven't dropped the series, will post it today. You prefer the
series on -rc1 or -rc2, not that it makes a difference.

regards
Suman

[PATCH 0/5] Use mmio-sram driver for Keystone MSMC RAM

[Santosh Shilimkar]

On 1/6/2017 11:10 AM, Suman Anna wrote:
> Hi Santosh,
>

>>> OK. Its good to add the code at least with one active user of it.
>>> Since this has to anyway wait for another merge window, please post the
>>> users of it so that I can pull the combined patchset.
>>>
>> Are you going to post new patchset or you dropped this series ?
>>
>> If you want me to include it for next merge window, please post
>> refreshed patchset.
>
> No, haven't dropped the series, will post it today. You prefer the
> series on -rc1 or -rc2, not that it makes a difference.
>
Right. rc1 is just fine.

Regards,
Sasntosh