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Mon, 08 Sep 2025 06:54:33 -0700 (PDT) Received: from [192.168.1.3] ([185.48.76.109]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45dd296ed51sm189909035e9.3.2025.09.08.06.54.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Sep 2025 06:54:33 -0700 (PDT) Message-ID: Date: Mon, 8 Sep 2025 14:54:32 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/3] perf: arm_spe: Add barrier before enabling profiling buffer To: Will Deacon Cc: Mark Rutland , Catalin Marinas , Alexandru Elisei , Anshuman Khandual , Rob Herring , Suzuki Poulose , Robin Murphy , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250701-james-spe-vm-interface-v1-0-52a2cd223d00@linaro.org> <20250701-james-spe-vm-interface-v1-1-52a2cd223d00@linaro.org> Content-Language: en-US From: James Clark In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250908_065435_115432_3D7B83FA X-CRM114-Status: GOOD ( 22.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 08/09/2025 2:41 pm, Will Deacon wrote: > On Tue, Jul 01, 2025 at 04:31:57PM +0100, James Clark wrote: >> DEN0154 states that PMBPTR_EL1 must not be modified while the profiling >> buffer is enabled. Ensure that enabling the buffer comes after setting >> PMBPTR_EL1 by inserting an isb(). >> >> This only applies to guests for now, but in future versions of the >> architecture the PE will be allowed to behave in the same way. >> >> Fixes: d5d9696b0380 ("drivers/perf: Add support for ARMv8.2 Statistical Profiling Extension") >> Signed-off-by: James Clark >> --- >> drivers/perf/arm_spe_pmu.c | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c >> index 3efed8839a4e..6235ca7ecd48 100644 >> --- a/drivers/perf/arm_spe_pmu.c >> +++ b/drivers/perf/arm_spe_pmu.c >> @@ -537,6 +537,7 @@ static void arm_spe_perf_aux_output_begin(struct perf_output_handle *handle, >> limit += (u64)buf->base; >> base = (u64)buf->base + PERF_IDX2OFF(handle->head, buf); >> write_sysreg_s(base, SYS_PMBPTR_EL1); >> + isb(); > > > Hmm. > > arm_spe_perf_aux_output_begin() is only called in two places: > > 1. From arm_spe_pmu_start() > 2. From arm_spe_pmu_irq_handler() > > For (1), we know that profiling is disabled by PMSCR_EL1.ExSPE. > For (2), we know that profiling is disabled by PMBSR_EL1.S. > > In both cases, we already have an isb() before enabling profiling again > so I don't understand what this additional isb() is achieving. > > Will It's to prevent PMBPTR_EL1 from being written to after the PMBLIMITR_EL1 write than enables the buffer again. So you're right it's already disabled up to this point, which is why we didn't need to add another isb(). This change is only for the re-enabling bit. If the instructions were reordered you could get this ordering at the end of arm_spe_perf_aux_output_begin(): write_sysreg_s(limit, SYS_PMBLIMITR_EL1); // Enables buffer write_sysreg_s(base, SYS_PMBPTR_EL1); // Invalid write to PMBPTR Instead of the new version with the barrier where PMBPTR must come before: write_sysreg_s(base, SYS_PMBPTR_EL1); isb() write_sysreg_s(limit, SYS_PMBLIMITR_EL1); Thanks James