From: yixun.lan@amlogic.com (Yixun Lan)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v7 6/6] arm64: dts: meson-axg: switch uart_ao clock to CLK81
Date: Fri, 15 Dec 2017 09:49:11 +0800 [thread overview]
Message-ID: <b4e29e22-c0e9-1085-fbb7-eabc5c361445@amlogic.com> (raw)
In-Reply-To: <1513270051.2261.11.camel@baylibre.com>
On 12/15/17 00:47, Jerome Brunet wrote:
> On Mon, 2017-12-11 at 22:13 +0800, Yixun Lan wrote:
>> Switch the uart_ao pclk to CLK81 since the clock driver is ready.
>> Also move the clock info to the board.dts instead in the soc.dtsi.
>
> Same comment as for ethmac, is it really wise ?
> Isn't the clock setup the same for the axg family ?
>
HI Jerome:
yes, should be same for AXG family
HI Kevin:
could you take the patch [5/6]? then I just need to resend for this one
Yixun
next prev parent reply other threads:[~2017-12-15 1:49 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-11 14:13 [PATCH v7 0/6] add clk controller driver for Meson-AXG SoC Yixun Lan
2017-12-11 14:13 ` [PATCH v7 1/6] clk: meson: make the spinlock naming more specific Yixun Lan
2017-12-14 9:57 ` Jerome Brunet
2017-12-11 14:13 ` [PATCH v7 2/6] dt-bindings: clock: add compatible variant for the Meson-AXG Yixun Lan
2017-12-14 9:57 ` Jerome Brunet
2017-12-11 14:13 ` [PATCH v7 3/6] clk: meson-axg: add clocks dt-bindings required header Yixun Lan
2017-12-14 9:58 ` Jerome Brunet
2017-12-11 14:13 ` [PATCH v7 4/6] clk: meson-axg: add clock controller drivers Yixun Lan
2017-12-14 9:59 ` Jerome Brunet
2017-12-11 14:13 ` [PATCH v7 5/6] arm64: dts: meson-axg: add clock DT info for Meson AXG SoC Yixun Lan
2017-12-15 18:58 ` Kevin Hilman
2017-12-11 14:13 ` [PATCH v7 6/6] arm64: dts: meson-axg: switch uart_ao clock to CLK81 Yixun Lan
2017-12-14 16:47 ` Jerome Brunet
2017-12-15 1:49 ` Yixun Lan [this message]
2017-12-15 19:14 ` Kevin Hilman
2017-12-14 10:03 ` [PATCH v7 0/6] add clk controller driver for Meson-AXG SoC Jerome Brunet
2017-12-14 10:11 ` Yixun Lan
2017-12-15 20:00 ` Kevin Hilman
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