Re: [PATCH 1/3] dt-bindings: gpu: img,powervr-rogue: Document GX6250 GPU in Renesas R-Car M3-W/M3-W+

[Matt Coster <Matt.Coster@imgtec.com>]

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Hi Geert, Marek:

On 15/10/2025 10:10, Geert Uytterhoeven wrote:
> Hi Marek,
> 
> On Wed, 15 Oct 2025 at 00:48, Marek Vasut <marek.vasut@mailbox.org> wrote:
>> On 10/14/25 1:52 PM, Matt Coster wrote:
>>>> diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
>>>> index c87d7bece0ecd..c9680a2560114 100644
>>>> --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
>>>> +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
>>>> @@ -13,6 +13,12 @@ maintainers:
>>>>   properties:
>>>>     compatible:
>>>>       oneOf:
>>>> +      - items:
>>>> +          - enum:
>>>> +              - renesas,r8a77960-gpu
>>>> +              - renesas,r8a77961-gpu
>>>
>>> I think this can just be renesas,r8a7796-gpu; most of the devices in the
>>> dts for these SoCs appear to use the same pattern and the GPU is the
>>> same in both.
>>
>> Not really, the 77960 and 77961 are different SoCs, that is why they
>> each have different specific compatible. Of course, most drivers match
>> on fallback compatible, since the IPs are mostly identical, see this:
>>
>> $ git grep compatible.*7796 arch/arm64/boot/dts/renesas/r8a77961.dtsi
>> arch/arm64/boot/dts/renesas/r8a77961.dtsi:      compatible =
>> "renesas,r8a77961";
>> arch/arm64/boot/dts/renesas/r8a77961.dtsi:
>> compatible = "renesas,r8a77961-wdt",
>> arch/arm64/boot/dts/renesas/r8a77961.dtsi:
>> compatible = "renesas,gpio-r8a77961",
>> ...
>>
>> $  git grep compatible.*7796 arch/arm64/boot/dts/renesas/r8a77960.dtsi
>> arch/arm64/boot/dts/renesas/r8a77960.dtsi:      compatible =
>> "renesas,r8a7796";
>> arch/arm64/boot/dts/renesas/r8a77960.dtsi:
>> compatible = "renesas,r8a7796-wdt",
>> arch/arm64/boot/dts/renesas/r8a77960.dtsi:
>> compatible = "renesas,gpio-r8a7796",
>> arch/arm64/boot/dts/renesas/r8a77960.dtsi:
>> compatible = "renesas,gpio-r8a7796",
>>
>> I can turn the first entry into renesas,r8a7796-gpu to be consistent
>> with the legacy 7796 name for 77960.
>>
>> Geert ?
> 
> Please use "renesas,r8a7796-gpu" for R-Car M3-W, and
> "renesas,r8a77961-gpu" for R-Car M3-W+.

Works for me. I mistook the non-0 version as a generic name for both,
not realising it was just a legacy thing. My bad!

> 
>>>> +          - const: img,img-gx6250
>>>> +          - const: img,img-rogue
>>>>         - items:
>>>>             - enum:
>>>>                 - ti,am62-gpu
>>>
>>> You also need to add img,img-gx6250 to the appropriate conditional
>>> blocks below here for the number of power domains (in this case, 2) and
>>> clocks (that's more complicated).
>>>
>>> These older GPUs always require three clocks (core, mem and sys), but
>>> it's not immediately clear from the Renesas TRM how these are hooked up.
>>> I can see three "clocks" connected (fig 23.2 in my copy, clock details
>>> from fig 8.1b):
>>
>> Which revision of the RM is that ? There should be some Rev.M.NP at the
>> bottom of each page.
> 
> Rev.2.40.

Yes, that's the version I have too.

> 
>>>   - Clock ZGφ: Appears to be a core clock for the GPU (3DGE). That would
>>>     make it our "core" clock.
>>
>> This should be 600-700 MHz clock on M3-W , so that sounds like a GPU
>> core clock.
> 
> Agreed.
> 
>>
>>>   - Clock S2D1φ: Appears to be a core clock used on the AXI bus, making
>>>     it our "sys" clock.
>>
>> This should be 400 MHz AXI clock, but wouldn't that make it "mem" clock
>> ? I think this might be the clock which drives the AXI bus, used by the
>> GPU to access data in DRAM ?
> 
> Agreed.
> 
>>>   - MSTP ST112: Appears to be a whole module on/off control of some
>>>     description, and definitely doesn't align with the missing "mem"
>>>     clock.
>>
>> Maybe this is the "sys" clock, since it toggles the register interface
>> clock on/off ?
> 
> Probably.

Yes, this is probably correct. I got my AXI interfaces mixed up – we
have both a manager interface for accessing memory (using the mem clock)
and a subordinate interface to expose to our registers (using the sys
clock). Here's the summary table from our system integration document:

   +-------+-------------------------+------------------------+
   | Clock | Modules Clocked         | Dependencies           |
   +-------+-------------------------+------------------------+
   | mem   | SLC / AXI Manager       | Run for all operations |
   | sys   | SOCIF / AXI Subordinate | Run for all operations |
   | core  | All                     | Run for all operations |
   +-------+-------------------------+------------------------+

Cheers,
Matt

> 
> Note that both ZGφ and S2D1φ are always-on.
> MSTP ST112 is the only gateable clock, and it is controlled through
> the PM Domain and Runtime PM.
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 

-- 
Matt Coster
E: matt.coster@imgtec.com

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