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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: xjfbg1Yy/iYYwtvd83QP/Vk6Hocsiv/I1Ary/USeBSBYiNUFps9tcYb291qUvUTFsCKvnYrWwronXu7aM+W+POFvYJM6/8qwZ3vTZcULs4fXFPVIbnYtWJ4nRldGqH1S29BQ70XiT2L5bnGHLOG7giBSbEXSL3e41hYKYwpIqxapCsOswAAxc1ukoMhd4/grxN3J7j5w8O8o7Qrm03q0jVS7JxVzbMFKCkxOgs3BBifMBbMiaAVbsycAXyOojETomiuDQOHNw5FzkUcDxDOeAEU+foMUJEKzQx/qJWDrEG/saOX5/Zo/TtCyqsaA+rRYsp2cjlRlYwJu/UWaSBHwT/OloJjlvenab6nCuIGq0/5BeHIOgUqUFfzsj1ugrrBAFqYUWFS4pTfutXcsI/DWTzduCPJ5QHGOUxCwwz9qQPIKWAzJ1zYaRRnrZOoWAKLS X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Mar 2026 15:02:22.3472 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 68c77ebb-a51f-4857-e86d-08de7935df94 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509E8.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB5325 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260303_070233_116963_2A5E220D X-CRM114-Status: GOOD ( 22.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 03/03/2026 14:39, Will Deacon wrote: > On Tue, Mar 03, 2026 at 09:48:06AM +0000, Suzuki K Poulose wrote: >> On 27/02/2026 21:21, Will Deacon wrote: >>> diff --git a/arch/arm64/kvm/hyp/nvhe/debug-sr.c b/arch/arm64/kvm/hyp/nvhe/debug-sr.c >>> index 3dbdee1148d3..75158a9cd06a 100644 >>> --- a/arch/arm64/kvm/hyp/nvhe/debug-sr.c >>> +++ b/arch/arm64/kvm/hyp/nvhe/debug-sr.c >>> @@ -14,20 +14,20 @@ >>> #include >>> #include >>> -static void __debug_save_spe(u64 *pmscr_el1) >>> +static void __debug_save_spe(void) >>> { >>> - u64 reg; >>> + u64 *pmscr_el1, *pmblimitr_el1; >>> - /* Clear pmscr in case of early return */ >>> - *pmscr_el1 = 0; >>> + pmscr_el1 = host_data_ptr(host_debug_state.pmscr_el1); >>> + pmblimitr_el1 = host_data_ptr(host_debug_state.pmblimitr_el1); >>> /* >>> * At this point, we know that this CPU implements >>> * SPE and is available to the host. >>> * Check if the host is actually using it ? >>> */ >>> - reg = read_sysreg_s(SYS_PMBLIMITR_EL1); >>> - if (!(reg & BIT(PMBLIMITR_EL1_E_SHIFT))) >>> + *pmblimitr_el1 = read_sysreg_s(SYS_PMBLIMITR_EL1); >>> + if (!(*pmblimitr_el1 & BIT(PMBLIMITR_EL1_E_SHIFT))) >>> return; >>> /* Yes; save the control register and disable data generation */ >>> @@ -37,18 +37,29 @@ static void __debug_save_spe(u64 *pmscr_el1) >>> /* Now drain all buffered data to memory */ >>> psb_csync(); >>> + dsb(nsh); >>> + >>> + /* And disable the profiling buffer */ >>> + write_sysreg_s(0, SYS_PMBLIMITR_EL1); >>> + isb(); >>> } >>> -static void __debug_restore_spe(u64 pmscr_el1) >>> +static void __debug_restore_spe(void) >>> { >>> - if (!pmscr_el1) >>> + u64 pmblimitr_el1 = *host_data_ptr(host_debug_state.pmblimitr_el1); >>> + >>> + if (!(pmblimitr_el1 & BIT(PMBLIMITR_EL1_E_SHIFT))) >>> return; >>> /* The host page table is installed, but not yet synchronised */ >>> isb(); >> >> minor nit: This seems buried deep down in a helper (with no context of what >> else could have happened since the host context has been restored) >> and for now it looks correct, but is prone to inadvertent changes >> causing issues or making this obsolete. With the isb() following LIMITR, >> wouldn't that be sufficient ? > > I'm just inherting this from the existing upstream code -- see the isb() > in the existing implementation of __debug_restore_spe(). Of course, it was. I should have added "not from your change". Now we have: __kvm_vcpu_run () { ..guest_exit.. //load_host_stage2() if required -> pkvm. __sysreg_restore_state_nvhe() -> __sysreg_restore_el1_state () #- we restore "host MMU context" here ... __debug_restore_host_buffers_nvhe() -> __debug_restore_spe(); #issue isb here to sync the host context } and the isb() is placed in the spe restore code. All of this is correct and I do understand why it is there. My comment was, this is not easily relatable and prone to errors with inadvertent changes (e.g., moving the spe around etc). But I agree that we can avoid the unconditional overhead over the code readability. Cheers Suzuki > > The isb() is needed to ensure that SPE can't start making out-of-context > translation table walks (which can occur once PMBLIMITR_EL1.E is set) > before the stage-2 MMU is restored back to the host configuration (e.g. > by clearing HCR_EL2.VM for nVHE or by restoring VTCR and VTTBR for > pKVM). We want to predicate it on SPE being enabled, otherwise it's > unconditional overhead, so I don't think we can move it. > > Will