[PATCH 0/3] Add support for MT8189 SCP and device tree bindings

[PATCH 0/3] Add support for MT8189 SCP and device tree bindings

[Huayu Zong]

  This patch series adds support for the System Companion
Processor (SCP) on MediaTek MT8189, including device tree
bindings, dts node, and driver support.

---
This series patches dependent on:
[1]
https://patchwork.kernel.org/project/linux-mediatek/cover/20250718075630.644870-1-sirius.wang@mediatek.com/

Huayu Zong (3):
  dt-bindings: remoteproc: mediatek: Add binding for mt8189 scp
  arm64: dts: mt8189: Add scp node
  remoteproc: mediatek: Support MT8189 SCP

 .../bindings/remoteproc/mtk,scp.yaml          |  2 +
 arch/arm64/boot/dts/mediatek/mt8189-evb.dts   | 17 +++++++++
 arch/arm64/boot/dts/mediatek/mt8189.dtsi      | 11 ++++++
 drivers/remoteproc/mtk_common.h               | 11 ++++++
 drivers/remoteproc/mtk_scp.c                  | 37 +++++++++++++++++--
 5 files changed, 75 insertions(+), 3 deletions(-)

-- 
2.45.2

[PATCH 1/3] dt-bindings: remoteproc: mediatek: Add binding for mt8189 scp

[Huayu Zong]

Add the compatible for mt8189 SCP to the binding.

Signed-off-by: Huayu Zong <huayu.zong@mediatek.com>
---
 Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml
index adc6b3f36fde..88e240430f3f 100644
--- a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml
+++ b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml
@@ -20,6 +20,7 @@ properties:
       - mediatek,mt8186-scp
       - mediatek,mt8188-scp
       - mediatek,mt8188-scp-dual
+      - mediatek,mt8189-scp
       - mediatek,mt8192-scp
       - mediatek,mt8195-scp
       - mediatek,mt8195-scp-dual
@@ -168,6 +169,7 @@ allOf:
             - mediatek,mt8183-scp
             - mediatek,mt8186-scp
             - mediatek,mt8188-scp
+            - mediatek,mt8189-scp
     then:
       properties:
         reg:
-- 
2.45.2

[PATCH 2/3] arm64: dts: mt8189: Add scp node

[Huayu Zong]

Add scp node for mt8189.

Signed-off-by: Huayu Zong <huayu.zong@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8189-evb.dts | 17 +++++++++++++++++
 arch/arm64/boot/dts/mediatek/mt8189.dtsi    | 11 +++++++++++
 2 files changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8189-evb.dts b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts
index e5d9ce1b8e61..39cd56b31ca0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8189-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts
@@ -13,8 +13,25 @@ / {
 	chosen: chosen {
 		stdout-path = "serial0:115200n8";
 	};
+
+	reserved_memory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		scp_mem_reserved: scp@50000000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0x50000000 0 0x2900000>;
+			no-map;
+		};
+	};
 };
 
 &uart0 {
 	status = "okay";
 };
+
+&scp {
+	status = "okay";
+	memory-region = <&scp_mem_reserved>;
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8189.dtsi b/arch/arm64/boot/dts/mediatek/mt8189.dtsi
index 2444c3e553ec..b70397b9ef6c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8189.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8189.dtsi
@@ -371,5 +371,16 @@ uart0: serial@11001000 {
 			clock-names = "baud", "bus";
 			status = "disabled";
 		};
+
+		scp: scp@1c400000 {
+			compatible = "mediatek,mt8189-scp";
+			reg = <0 0x1c400000 0 0x60000>,
+			      <0 0x1cb20000 0 0xe0000>;
+			reg-names = "sram", "cfg";
+			interrupts = <GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH 0>;
+			status = "disabled";
+			clocks = <&vlp_cksys_clk CLK_VLP_CK_SCP_SEL>;
+			clock-names = "scp_sel";
+		};
 	};
 };
-- 
2.45.2

[PATCH 3/3] remoteproc: mediatek: Support MT8189 SCP

[Huayu Zong]

Add SCP support for mt8189.

Signed-off-by: Huayu Zong <huayu.zong@mediatek.com>
---
 drivers/remoteproc/mtk_common.h | 11 ++++++++++
 drivers/remoteproc/mtk_scp.c    | 37 ++++++++++++++++++++++++++++++---
 2 files changed, 45 insertions(+), 3 deletions(-)

diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h
index fd5c539ab2ac..fb2131e0ed07 100644
--- a/drivers/remoteproc/mtk_common.h
+++ b/drivers/remoteproc/mtk_common.h
@@ -35,6 +35,11 @@
 #define MT8186_SCP_L1_SRAM_PD_P1	0x40B0
 #define MT8186_SCP_L1_SRAM_PD_p2	0x40B4
 
+#define MT8189_SCP2APMCU_IPC_CLR	0x30010
+#define MT8189_SCP2SPM_IPC_CLR		0x30018
+#define MT8189_SCP_SECURE_DOMAIN	0xA080
+#define MT8189_SCP_DOMAIN_VAL		0x3303003
+
 #define MT8192_L2TCM_SRAM_PD_0		0x10C0
 #define MT8192_L2TCM_SRAM_PD_1		0x10C4
 #define MT8192_L2TCM_SRAM_PD_2		0x10C8
@@ -112,6 +117,12 @@ struct mtk_scp_of_data {
 
 	u32 host_to_scp_reg;
 	u32 host_to_scp_int_bit;
+	u32 scp_to_host_ipc_set_reg;
+	u32 scp_to_host_ipc_clr_reg;
+	u32 scp_to_spm_ipc_clr_reg;
+
+	u32 scp_secure_domain_reg;
+	u32 scp_domain_value;
 
 	size_t ipi_buf_offset;
 	const struct mtk_scp_sizes_data *scp_sizes;
diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c
index 8206a1766481..956793fc6901 100644
--- a/drivers/remoteproc/mtk_scp.c
+++ b/drivers/remoteproc/mtk_scp.c
@@ -225,7 +225,8 @@ static void mt8192_scp_irq_handler(struct mtk_scp *scp)
 {
 	u32 scp_to_host;
 
-	scp_to_host = readl(scp->cluster->reg_base + MT8192_SCP2APMCU_IPC_SET);
+	scp_to_host = readl(scp->cluster->reg_base +
+			    scp->data->scp_to_host_ipc_set_reg);
 
 	if (scp_to_host & MT8192_SCP_IPC_INT_BIT) {
 		scp_ipi_handler(scp);
@@ -235,7 +236,7 @@ static void mt8192_scp_irq_handler(struct mtk_scp *scp)
 		 * MT8192_SCP2APMCU_IPC.
 		 */
 		writel(MT8192_SCP_IPC_INT_BIT,
-		       scp->cluster->reg_base + MT8192_SCP2APMCU_IPC_CLR);
+		       scp->cluster->reg_base + scp->data->scp_to_host_ipc_clr_reg);
 	} else {
 		scp_wdt_handler(scp, scp_to_host);
 		writel(1, scp->cluster->reg_base + MT8192_CORE0_WDT_IRQ);
@@ -559,8 +560,10 @@ static int mt8188_scp_c1_before_load(struct mtk_scp *scp)
 
 static int mt8192_scp_before_load(struct mtk_scp *scp)
 {
+	u32 scp2spm_ipc_clr = scp->data->scp_to_spm_ipc_clr_reg;
+
 	/* clear SPM interrupt, SCP2SPM_IPC_CLR */
-	writel(0xff, scp->cluster->reg_base + MT8192_SCP2SPM_IPC_CLR);
+	writel(0xff, scp->cluster->reg_base + scp2spm_ipc_clr);
 
 	writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_SET);
 
@@ -574,6 +577,11 @@ static int mt8192_scp_before_load(struct mtk_scp *scp)
 	/* enable MPU for all memory regions */
 	writel(0xff, scp->cluster->reg_base + MT8192_CORE0_MEM_ATT_PREDEF);
 
+	/* set the domain of master in SCP */
+	if (scp->data->scp_secure_domain_reg)
+		writel(scp->data->scp_domain_value,
+		       scp->cluster->reg_base + scp->data->scp_secure_domain_reg);
+
 	return 0;
 }
 
@@ -1464,6 +1472,24 @@ static const struct mtk_scp_of_data mt8188_of_data_c1 = {
 	.scp_sizes = &mt8188_scp_c1_sizes,
 };
 
+static const struct mtk_scp_of_data mt8189_of_data = {
+	.scp_clk_get = mt8195_scp_clk_get,
+	.scp_before_load = mt8192_scp_before_load,
+	.scp_irq_handler = mt8192_scp_irq_handler,
+	.scp_reset_assert = mt8192_scp_reset_assert,
+	.scp_reset_deassert = mt8192_scp_reset_deassert,
+	.scp_stop = mt8192_scp_stop,
+	.scp_da_to_va = mt8192_scp_da_to_va,
+	.host_to_scp_reg = MT8192_GIPC_IN_SET,
+	.host_to_scp_int_bit = MT8192_HOST_IPC_INT_BIT,
+	.scp_to_host_ipc_set_reg = MT8192_SCP2APMCU_IPC_SET,
+	.scp_to_host_ipc_clr_reg = MT8189_SCP2APMCU_IPC_CLR,
+	.scp_to_spm_ipc_clr_reg = MT8189_SCP2SPM_IPC_CLR,
+	.scp_secure_domain_reg = MT8189_SCP_SECURE_DOMAIN,
+	.scp_domain_value = MT8189_SCP_DOMAIN_VAL,
+	.scp_sizes = &default_scp_sizes,
+};
+
 static const struct mtk_scp_of_data mt8192_of_data = {
 	.scp_clk_get = mt8192_scp_clk_get,
 	.scp_before_load = mt8192_scp_before_load,
@@ -1475,6 +1501,10 @@ static const struct mtk_scp_of_data mt8192_of_data = {
 	.host_to_scp_reg = MT8192_GIPC_IN_SET,
 	.host_to_scp_int_bit = MT8192_HOST_IPC_INT_BIT,
 	.scp_sizes = &default_scp_sizes,
+	.scp_to_host_ipc_set_reg = MT8192_SCP2APMCU_IPC_SET,
+	.scp_to_host_ipc_clr_reg = MT8192_SCP2APMCU_IPC_CLR,
+	.scp_to_spm_ipc_clr_reg = MT8192_SCP2SPM_IPC_CLR,
+	.scp_sizes = &default_scp_sizes,
 };
 
 static const struct mtk_scp_of_data mt8195_of_data = {
@@ -1520,6 +1550,7 @@ static const struct of_device_id mtk_scp_of_match[] = {
 	{ .compatible = "mediatek,mt8186-scp", .data = &mt8186_of_data },
 	{ .compatible = "mediatek,mt8188-scp", .data = &mt8188_of_data },
 	{ .compatible = "mediatek,mt8188-scp-dual", .data = &mt8188_of_data_cores },
+	{ .compatible = "mediatek,mt8189-scp", .data = &mt8189_of_data },
 	{ .compatible = "mediatek,mt8192-scp", .data = &mt8192_of_data },
 	{ .compatible = "mediatek,mt8195-scp", .data = &mt8195_of_data },
 	{ .compatible = "mediatek,mt8195-scp-dual", .data = &mt8195_of_data_cores },
-- 
2.45.2

Re: [PATCH 1/3] dt-bindings: remoteproc: mediatek: Add binding for mt8189 scp

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 228 bytes --]

On Tue, Jul 29, 2025 at 10:31:11AM +0800, Huayu Zong wrote:
> Add the compatible for mt8189 SCP to the binding.
> 
> Signed-off-by: Huayu Zong <huayu.zong@mediatek.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH 3/3] remoteproc: mediatek: Support MT8189 SCP

[Mathieu Poirier]

Hi,

On Tue, Jul 29, 2025 at 10:31:13AM +0800, Huayu Zong wrote:
> Add SCP support for mt8189.
> 
> Signed-off-by: Huayu Zong <huayu.zong@mediatek.com>
> ---
>  drivers/remoteproc/mtk_common.h | 11 ++++++++++
>  drivers/remoteproc/mtk_scp.c    | 37 ++++++++++++++++++++++++++++++---
>  2 files changed, 45 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h
> index fd5c539ab2ac..fb2131e0ed07 100644
> --- a/drivers/remoteproc/mtk_common.h
> +++ b/drivers/remoteproc/mtk_common.h
> @@ -35,6 +35,11 @@
>  #define MT8186_SCP_L1_SRAM_PD_P1	0x40B0
>  #define MT8186_SCP_L1_SRAM_PD_p2	0x40B4
>  
> +#define MT8189_SCP2APMCU_IPC_CLR	0x30010
> +#define MT8189_SCP2SPM_IPC_CLR		0x30018
> +#define MT8189_SCP_SECURE_DOMAIN	0xA080
> +#define MT8189_SCP_DOMAIN_VAL		0x3303003
> +
>  #define MT8192_L2TCM_SRAM_PD_0		0x10C0
>  #define MT8192_L2TCM_SRAM_PD_1		0x10C4
>  #define MT8192_L2TCM_SRAM_PD_2		0x10C8
> @@ -112,6 +117,12 @@ struct mtk_scp_of_data {
>  
>  	u32 host_to_scp_reg;
>  	u32 host_to_scp_int_bit;
> +	u32 scp_to_host_ipc_set_reg;
> +	u32 scp_to_host_ipc_clr_reg;
> +	u32 scp_to_spm_ipc_clr_reg;
> +
> +	u32 scp_secure_domain_reg;
> +	u32 scp_domain_value;
>  
>  	size_t ipi_buf_offset;
>  	const struct mtk_scp_sizes_data *scp_sizes;
> diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c
> index 8206a1766481..956793fc6901 100644
> --- a/drivers/remoteproc/mtk_scp.c
> +++ b/drivers/remoteproc/mtk_scp.c
> @@ -225,7 +225,8 @@ static void mt8192_scp_irq_handler(struct mtk_scp *scp)
>  {
>  	u32 scp_to_host;
>  
> -	scp_to_host = readl(scp->cluster->reg_base + MT8192_SCP2APMCU_IPC_SET);
> +	scp_to_host = readl(scp->cluster->reg_base +
> +			    scp->data->scp_to_host_ipc_set_reg);

As far as I can tell, this is the same for both mt8189 and mt8192 - it should
not be needed.

>  
>  	if (scp_to_host & MT8192_SCP_IPC_INT_BIT) {
>  		scp_ipi_handler(scp);
> @@ -235,7 +236,7 @@ static void mt8192_scp_irq_handler(struct mtk_scp *scp)
>  		 * MT8192_SCP2APMCU_IPC.
>  		 */
>  		writel(MT8192_SCP_IPC_INT_BIT,
> -		       scp->cluster->reg_base + MT8192_SCP2APMCU_IPC_CLR);
> +		       scp->cluster->reg_base + scp->data->scp_to_host_ipc_clr_reg);
>  	} else {
>  		scp_wdt_handler(scp, scp_to_host);
>  		writel(1, scp->cluster->reg_base + MT8192_CORE0_WDT_IRQ);
> @@ -559,8 +560,10 @@ static int mt8188_scp_c1_before_load(struct mtk_scp *scp)
>  
>  static int mt8192_scp_before_load(struct mtk_scp *scp)
>  {
> +	u32 scp2spm_ipc_clr = scp->data->scp_to_spm_ipc_clr_reg;
> +
>  	/* clear SPM interrupt, SCP2SPM_IPC_CLR */
> -	writel(0xff, scp->cluster->reg_base + MT8192_SCP2SPM_IPC_CLR);
> +	writel(0xff, scp->cluster->reg_base + scp2spm_ipc_clr);
>  
>  	writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_SET);
>  
> @@ -574,6 +577,11 @@ static int mt8192_scp_before_load(struct mtk_scp *scp)
>  	/* enable MPU for all memory regions */
>  	writel(0xff, scp->cluster->reg_base + MT8192_CORE0_MEM_ATT_PREDEF);
>  
> +	/* set the domain of master in SCP */
> +	if (scp->data->scp_secure_domain_reg)
> +		writel(scp->data->scp_domain_value,
> +		       scp->cluster->reg_base + scp->data->scp_secure_domain_reg);
> +
>  	return 0;
>  }
>  
> @@ -1464,6 +1472,24 @@ static const struct mtk_scp_of_data mt8188_of_data_c1 = {
>  	.scp_sizes = &mt8188_scp_c1_sizes,
>  };
>  
> +static const struct mtk_scp_of_data mt8189_of_data = {
> +	.scp_clk_get = mt8195_scp_clk_get,
> +	.scp_before_load = mt8192_scp_before_load,
> +	.scp_irq_handler = mt8192_scp_irq_handler,
> +	.scp_reset_assert = mt8192_scp_reset_assert,
> +	.scp_reset_deassert = mt8192_scp_reset_deassert,
> +	.scp_stop = mt8192_scp_stop,
> +	.scp_da_to_va = mt8192_scp_da_to_va,
> +	.host_to_scp_reg = MT8192_GIPC_IN_SET,
> +	.host_to_scp_int_bit = MT8192_HOST_IPC_INT_BIT,
> +	.scp_to_host_ipc_set_reg = MT8192_SCP2APMCU_IPC_SET,
> +	.scp_to_host_ipc_clr_reg = MT8189_SCP2APMCU_IPC_CLR,
> +	.scp_to_spm_ipc_clr_reg = MT8189_SCP2SPM_IPC_CLR,
> +	.scp_secure_domain_reg = MT8189_SCP_SECURE_DOMAIN,
> +	.scp_domain_value = MT8189_SCP_DOMAIN_VAL,
> +	.scp_sizes = &default_scp_sizes,
> +};
> +
>  static const struct mtk_scp_of_data mt8192_of_data = {
>  	.scp_clk_get = mt8192_scp_clk_get,
>  	.scp_before_load = mt8192_scp_before_load,
> @@ -1475,6 +1501,10 @@ static const struct mtk_scp_of_data mt8192_of_data = {
>  	.host_to_scp_reg = MT8192_GIPC_IN_SET,
>  	.host_to_scp_int_bit = MT8192_HOST_IPC_INT_BIT,
>  	.scp_sizes = &default_scp_sizes,
> +	.scp_to_host_ipc_set_reg = MT8192_SCP2APMCU_IPC_SET,
> +	.scp_to_host_ipc_clr_reg = MT8192_SCP2APMCU_IPC_CLR,
> +	.scp_to_spm_ipc_clr_reg = MT8192_SCP2SPM_IPC_CLR,
> +	.scp_sizes = &default_scp_sizes,

You are introducing a duplicate .scp_sizes

Thanks,
Mathieu

>  };
>  
>  static const struct mtk_scp_of_data mt8195_of_data = {
> @@ -1520,6 +1550,7 @@ static const struct of_device_id mtk_scp_of_match[] = {
>  	{ .compatible = "mediatek,mt8186-scp", .data = &mt8186_of_data },
>  	{ .compatible = "mediatek,mt8188-scp", .data = &mt8188_of_data },
>  	{ .compatible = "mediatek,mt8188-scp-dual", .data = &mt8188_of_data_cores },
> +	{ .compatible = "mediatek,mt8189-scp", .data = &mt8189_of_data },
>  	{ .compatible = "mediatek,mt8192-scp", .data = &mt8192_of_data },
>  	{ .compatible = "mediatek,mt8195-scp", .data = &mt8195_of_data },
>  	{ .compatible = "mediatek,mt8195-scp-dual", .data = &mt8195_of_data_cores },
> -- 
> 2.45.2
> 

Re: [PATCH 3/3] remoteproc: mediatek: Support MT8189 SCP

[Huayu Zong (纵华宇)]

On Wed, 2025-07-30 at 09:07 -0600, Mathieu Poirier wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> Hi,
> 
> On Tue, Jul 29, 2025 at 10:31:13AM +0800, Huayu Zong wrote:
> > Add SCP support for mt8189.
> > 
> > Signed-off-by: Huayu Zong <huayu.zong@mediatek.com>
> > ---
> >  drivers/remoteproc/mtk_common.h | 11 ++++++++++
> >  drivers/remoteproc/mtk_scp.c    | 37
> > ++++++++++++++++++++++++++++++---
> >  2 files changed, 45 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/remoteproc/mtk_common.h
> > b/drivers/remoteproc/mtk_common.h
> > index fd5c539ab2ac..fb2131e0ed07 100644
> > --- a/drivers/remoteproc/mtk_common.h
> > +++ b/drivers/remoteproc/mtk_common.h
> > @@ -35,6 +35,11 @@
> >  #define MT8186_SCP_L1_SRAM_PD_P1     0x40B0
> >  #define MT8186_SCP_L1_SRAM_PD_p2     0x40B4
> > 
> > +#define MT8189_SCP2APMCU_IPC_CLR     0x30010
> > +#define MT8189_SCP2SPM_IPC_CLR               0x30018
> > +#define MT8189_SCP_SECURE_DOMAIN     0xA080
> > +#define MT8189_SCP_DOMAIN_VAL                0x3303003
> > +
> >  #define MT8192_L2TCM_SRAM_PD_0               0x10C0
> >  #define MT8192_L2TCM_SRAM_PD_1               0x10C4
> >  #define MT8192_L2TCM_SRAM_PD_2               0x10C8
> > @@ -112,6 +117,12 @@ struct mtk_scp_of_data {
> > 
> >       u32 host_to_scp_reg;
> >       u32 host_to_scp_int_bit;
> > +     u32 scp_to_host_ipc_set_reg;
> > +     u32 scp_to_host_ipc_clr_reg;
> > +     u32 scp_to_spm_ipc_clr_reg;
> > +
> > +     u32 scp_secure_domain_reg;
> > +     u32 scp_domain_value;
> > 
> >       size_t ipi_buf_offset;
> >       const struct mtk_scp_sizes_data *scp_sizes;
> > diff --git a/drivers/remoteproc/mtk_scp.c
> > b/drivers/remoteproc/mtk_scp.c
> > index 8206a1766481..956793fc6901 100644
> > --- a/drivers/remoteproc/mtk_scp.c
> > +++ b/drivers/remoteproc/mtk_scp.c
> > @@ -225,7 +225,8 @@ static void mt8192_scp_irq_handler(struct
> > mtk_scp *scp)
> >  {
> >       u32 scp_to_host;
> > 
> > -     scp_to_host = readl(scp->cluster->reg_base +
> > MT8192_SCP2APMCU_IPC_SET);
> > +     scp_to_host = readl(scp->cluster->reg_base +
> > +                         scp->data->scp_to_host_ipc_set_reg);
> 
> As far as I can tell, this is the same for both mt8189 and mt8192 -
> it should
> not be needed.
> 

Thanks, I will update it in next version patch.

> > 
> >       if (scp_to_host & MT8192_SCP_IPC_INT_BIT) {
> >               scp_ipi_handler(scp);
> > @@ -235,7 +236,7 @@ static void mt8192_scp_irq_handler(struct
> > mtk_scp *scp)
> >                * MT8192_SCP2APMCU_IPC.
> >                */
> >               writel(MT8192_SCP_IPC_INT_BIT,
> > -                    scp->cluster->reg_base +
> > MT8192_SCP2APMCU_IPC_CLR);
> > +                    scp->cluster->reg_base + scp->data-
> > >scp_to_host_ipc_clr_reg);
> >       } else {
> >               scp_wdt_handler(scp, scp_to_host);
> >               writel(1, scp->cluster->reg_base +
> > MT8192_CORE0_WDT_IRQ);
> > @@ -559,8 +560,10 @@ static int mt8188_scp_c1_before_load(struct
> > mtk_scp *scp)
> > 
> >  static int mt8192_scp_before_load(struct mtk_scp *scp)
> >  {
> > +     u32 scp2spm_ipc_clr = scp->data->scp_to_spm_ipc_clr_reg;
> > +
> >       /* clear SPM interrupt, SCP2SPM_IPC_CLR */
> > -     writel(0xff, scp->cluster->reg_base +
> > MT8192_SCP2SPM_IPC_CLR);
> > +     writel(0xff, scp->cluster->reg_base + scp2spm_ipc_clr);
> > 
> >       writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_SET);
> > 
> > @@ -574,6 +577,11 @@ static int mt8192_scp_before_load(struct
> > mtk_scp *scp)
> >       /* enable MPU for all memory regions */
> >       writel(0xff, scp->cluster->reg_base +
> > MT8192_CORE0_MEM_ATT_PREDEF);
> > 
> > +     /* set the domain of master in SCP */
> > +     if (scp->data->scp_secure_domain_reg)
> > +             writel(scp->data->scp_domain_value,
> > +                    scp->cluster->reg_base + scp->data-
> > >scp_secure_domain_reg);
> > +
> >       return 0;
> >  }
> > 
> > @@ -1464,6 +1472,24 @@ static const struct mtk_scp_of_data
> > mt8188_of_data_c1 = {
> >       .scp_sizes = &mt8188_scp_c1_sizes,
> >  };
> > 
> > +static const struct mtk_scp_of_data mt8189_of_data = {
> > +     .scp_clk_get = mt8195_scp_clk_get,
> > +     .scp_before_load = mt8192_scp_before_load,
> > +     .scp_irq_handler = mt8192_scp_irq_handler,
> > +     .scp_reset_assert = mt8192_scp_reset_assert,
> > +     .scp_reset_deassert = mt8192_scp_reset_deassert,
> > +     .scp_stop = mt8192_scp_stop,
> > +     .scp_da_to_va = mt8192_scp_da_to_va,
> > +     .host_to_scp_reg = MT8192_GIPC_IN_SET,
> > +     .host_to_scp_int_bit = MT8192_HOST_IPC_INT_BIT,
> > +     .scp_to_host_ipc_set_reg = MT8192_SCP2APMCU_IPC_SET,
> > +     .scp_to_host_ipc_clr_reg = MT8189_SCP2APMCU_IPC_CLR,
> > +     .scp_to_spm_ipc_clr_reg = MT8189_SCP2SPM_IPC_CLR,
> > +     .scp_secure_domain_reg = MT8189_SCP_SECURE_DOMAIN,
> > +     .scp_domain_value = MT8189_SCP_DOMAIN_VAL,
> > +     .scp_sizes = &default_scp_sizes,
> > +};
> > +
> >  static const struct mtk_scp_of_data mt8192_of_data = {
> >       .scp_clk_get = mt8192_scp_clk_get,
> >       .scp_before_load = mt8192_scp_before_load,
> > @@ -1475,6 +1501,10 @@ static const struct mtk_scp_of_data
> > mt8192_of_data = {
> >       .host_to_scp_reg = MT8192_GIPC_IN_SET,
> >       .host_to_scp_int_bit = MT8192_HOST_IPC_INT_BIT,
> >       .scp_sizes = &default_scp_sizes,
> > +     .scp_to_host_ipc_set_reg = MT8192_SCP2APMCU_IPC_SET,
> > +     .scp_to_host_ipc_clr_reg = MT8192_SCP2APMCU_IPC_CLR,
> > +     .scp_to_spm_ipc_clr_reg = MT8192_SCP2SPM_IPC_CLR,
> > +     .scp_sizes = &default_scp_sizes,
> 
> You are introducing a duplicate .scp_sizes
> 
> Thanks,
> Mathieu
> 

Thanks, I will remove the duplicate .scp_sizes in mt8192_of_data.

> >  };
> > 
> >  static const struct mtk_scp_of_data mt8195_of_data = {
> > @@ -1520,6 +1550,7 @@ static const struct of_device_id
> > mtk_scp_of_match[] = {
> >       { .compatible = "mediatek,mt8186-scp", .data =
> > &mt8186_of_data },
> >       { .compatible = "mediatek,mt8188-scp", .data =
> > &mt8188_of_data },
> >       { .compatible = "mediatek,mt8188-scp-dual", .data =
> > &mt8188_of_data_cores },
> > +     { .compatible = "mediatek,mt8189-scp", .data =
> > &mt8189_of_data },
> >       { .compatible = "mediatek,mt8192-scp", .data =
> > &mt8192_of_data },
> >       { .compatible = "mediatek,mt8195-scp", .data =
> > &mt8195_of_data },
> >       { .compatible = "mediatek,mt8195-scp-dual", .data =
> > &mt8195_of_data_cores },
> > --
> > 2.45.2
> > 

Re: [PATCH 1/3] dt-bindings: remoteproc: mediatek: Add binding for mt8189 scp

[AngeloGioacchino Del Regno]

Il 29/07/25 04:31, Huayu Zong ha scritto:
> Add the compatible for mt8189 SCP to the binding.
> 
> Signed-off-by: Huayu Zong <huayu.zong@mediatek.com>

Is MT8189's SCP really single-core?

All of the new SoCs have two SCP cores - it's a bit strange to see that 8189 has
only one... hence, please triple check and confirm.

Cheers,
Angelo

> ---
>   Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml
> index adc6b3f36fde..88e240430f3f 100644
> --- a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml
> +++ b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml
> @@ -20,6 +20,7 @@ properties:
>         - mediatek,mt8186-scp
>         - mediatek,mt8188-scp
>         - mediatek,mt8188-scp-dual
> +      - mediatek,mt8189-scp
>         - mediatek,mt8192-scp
>         - mediatek,mt8195-scp
>         - mediatek,mt8195-scp-dual
> @@ -168,6 +169,7 @@ allOf:
>               - mediatek,mt8183-scp
>               - mediatek,mt8186-scp
>               - mediatek,mt8188-scp
> +            - mediatek,mt8189-scp
>       then:
>         properties:
>           reg:

Re: [PATCH 1/3] dt-bindings: remoteproc: mediatek: Add binding for mt8189 scp

[Huayu Zong (纵华宇)]

On Mon, 2025-08-04 at 10:27 +0200, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> Il 29/07/25 04:31, Huayu Zong ha scritto:
> > Add the compatible for mt8189 SCP to the binding.
> > 
> > Signed-off-by: Huayu Zong <huayu.zong@mediatek.com>
> 
> Is MT8189's SCP really single-core?
> 
> All of the new SoCs have two SCP cores - it's a bit strange to see
> that 8189 has
> only one... hence, please triple check and confirm.
> 
> Cheers,
> Angelo
> 

yes. On the 8189 platform, the architecture design of SCP is a single
core.

> > ---
> >   Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml | 2 ++
> >   1 file changed, 2 insertions(+)
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml
> > b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml
> > index adc6b3f36fde..88e240430f3f 100644
> > --- a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml
> > +++ b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml
> > @@ -20,6 +20,7 @@ properties:
> >         - mediatek,mt8186-scp
> >         - mediatek,mt8188-scp
> >         - mediatek,mt8188-scp-dual
> > +      - mediatek,mt8189-scp
> >         - mediatek,mt8192-scp
> >         - mediatek,mt8195-scp
> >         - mediatek,mt8195-scp-dual
> > @@ -168,6 +169,7 @@ allOf:
> >               - mediatek,mt8183-scp
> >               - mediatek,mt8186-scp
> >               - mediatek,mt8188-scp
> > +            - mediatek,mt8189-scp
> >       then:
> >         properties:
> >           reg:
> 
> 
> 

Re: [PATCH 1/3] dt-bindings: remoteproc: mediatek: Add binding for mt8189 scp

[AngeloGioacchino Del Regno]

Il 04/08/25 11:10, Huayu Zong (纵华宇) ha scritto:
> On Mon, 2025-08-04 at 10:27 +0200, AngeloGioacchino Del Regno wrote:
>> External email : Please do not click links or open attachments until
>> you have verified the sender or the content.
>>
>>
>> Il 29/07/25 04:31, Huayu Zong ha scritto:
>>> Add the compatible for mt8189 SCP to the binding.
>>>
>>> Signed-off-by: Huayu Zong <huayu.zong@mediatek.com>
>>
>> Is MT8189's SCP really single-core?
>>
>> All of the new SoCs have two SCP cores - it's a bit strange to see
>> that 8189 has
>> only one... hence, please triple check and confirm.
>>
>> Cheers,
>> Angelo
>>
> 
> yes. On the 8189 platform, the architecture design of SCP is a single
> core.
> 

By hardware, or because the firmware uses only one core?

I'm asking again because this happened multiple times - with MT8195 and MT8188.

If this is by hardware:

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Re: [PATCH 1/3] dt-bindings: remoteproc: mediatek: Add binding for mt8189 scp

[Huayu Zong (纵华宇)]

On Mon, 2025-08-04 at 11:11 +0200, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> Il 04/08/25 11:10, Huayu Zong (纵华宇) ha scritto:
> > On Mon, 2025-08-04 at 10:27 +0200, AngeloGioacchino Del Regno
> > wrote:
> > > External email : Please do not click links or open attachments
> > > until
> > > you have verified the sender or the content.
> > > 
> > > 
> > > Il 29/07/25 04:31, Huayu Zong ha scritto:
> > > > Add the compatible for mt8189 SCP to the binding.
> > > > 
> > > > Signed-off-by: Huayu Zong <huayu.zong@mediatek.com>
> > > 
> > > Is MT8189's SCP really single-core?
> > > 
> > > All of the new SoCs have two SCP cores - it's a bit strange to
> > > see
> > > that 8189 has
> > > only one... hence, please triple check and confirm.
> > > 
> > > Cheers,
> > > Angelo
> > > 
> > 
> > yes. On the 8189 platform, the architecture design of SCP is a
> > single
> > core.
> > 
> 
> By hardware, or because the firmware uses only one core?
> 
> I'm asking again because this happened multiple times - with MT8195
> and MT8188.
> 
> If this is by hardware:
> 
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> 
> 

MT8189 SCP hardware has only on core, not SW determinate.

On both MT8188 and MT8195 SCP platform, they have two cores. But there
are fewer features running on the 8189 SCP, so its hardware is designed
with just one core.

Thanks.