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From: Steve Clevenger <scclevenger@os.amperecomputing.com>
To: James Clark <james.clark@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	mathieu.poirier@linaro.org
Cc: mike.leach@linaro.org, coresight@lists.linaro.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 2/3] coresight etm4x: Add 32-bit read/write option to split 64-bit words
Date: Mon, 6 Mar 2023 17:24:07 -0800	[thread overview]
Message-ID: <b72c8f83-2270-de7d-b7a9-e2da235c010e@os.amperecomputing.com> (raw)
In-Reply-To: <7ef3a643-60a4-6cdc-cb48-de0f727a4798@arm.com>


Hi James,

Thanks for the feedback. I did hide the split 64-bit implementation
under the generic helpers. Note these helpers are now static inline code
instead of macro implementations. This significantly reduced the number
of changes where the etm4x_relaxed write64 and etm4x_relaxed_read64
calls were used.

Steve

On 3/6/2023 2:37 AM, James Clark wrote:
> 
> 
> On 20/01/2023 11:19, Suzuki K Poulose wrote:
>> On 20/01/2023 00:51, Steve Clevenger wrote:
> [...]
>>>       }
>>> -    for (i = 0; i < drvdata->nr_addr_cmp; i++) {
>>> -        etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i));
>>> -        etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i));
>>> +    for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
>>> +        if (drvdata->no_quad_mmio) {
>>> +            etm4x_split_write64(csa, config->addr_val[i], TRCACVRn(i));
>>> +            etm4x_split_write64(csa, config->addr_acc[i], TRCACATRn(i));
>>> +        } else {
>>> +            etm4x_relaxed_write64(csa, config->addr_val[i],
>>> TRCACVRn(i));
>>> +            etm4x_relaxed_write64(csa, config->addr_acc[i],
>>> TRCACATRn(i));
>>> +        }
>>> +    }
>>
>> Something like this can be leave some places out. I think we could hide
>> it under the generic helpers and handle it there. May be "struct
>> csdev_access" can cache this "no_quad_mmio" and do the right thing ?
> 
> +1 for this, or just pass drvdata to etm4x_relaxed_write64() and then it
> can decide what to do. I'd prefer that to caching the value in
> csdev_access because it would just be a copy of some other value and
> might go stale or not be set at some point.
> 
> James

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  reply	other threads:[~2023-03-07  1:25 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-20  0:51 [PATCH 0/3] Ampere Computing ETMv4.x Support Steve Clevenger
2023-01-20  0:51 ` [PATCH 1/3] coresight etm4x: Early clear TRCOSLAR.OSLK prior to TRCIDR1 read Steve Clevenger
2023-01-20 11:12   ` Suzuki K Poulose
2023-01-21  7:30     ` Steve Clevenger
2023-01-23 10:54       ` Suzuki K Poulose
2023-01-23 17:22         ` Steve Clevenger
2023-01-23 17:33           ` Suzuki K Poulose
2023-01-23 19:48             ` Steve Clevenger
2023-01-23 22:18               ` Suzuki K Poulose
2023-01-23 22:51                 ` Suzuki K Poulose
2023-02-02  5:20                   ` Steve Clevenger
2023-02-02 11:16                     ` Suzuki K Poulose
2023-02-02 17:12                       ` Steve Clevenger
2023-02-02 17:27                         ` Suzuki K Poulose
2023-02-02 23:03                           ` Steve Clevenger
2023-03-01 10:01                             ` Suzuki K Poulose
2023-01-20 11:45   ` Mike Leach
2023-01-21  7:31     ` Steve Clevenger
2023-01-23 10:54       ` Mike Leach
2023-01-23 19:47         ` Steve Clevenger
2023-01-23 22:49           ` Suzuki K Poulose
2023-01-20  0:51 ` [PATCH 2/3] coresight etm4x: Add 32-bit read/write option to split 64-bit words Steve Clevenger
2023-01-20 11:19   ` Suzuki K Poulose
2023-01-22  8:32     ` Steve Clevenger
2023-01-23 17:58       ` Suzuki K Poulose
2023-03-06 10:37     ` James Clark
2023-03-07  1:24       ` Steve Clevenger [this message]
2023-01-20  0:51 ` [PATCH 3/3] coresight etm4x: Add pr_debug statement for Coresight component PID/CID Steve Clevenger
2023-01-20 11:23   ` Suzuki K Poulose
2023-01-20 12:40     ` Russell King (Oracle)
2023-01-21  7:31       ` Steve Clevenger

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