From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2393FC4332F for ; Tue, 18 Jan 2022 03:16:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date: Message-ID:From:References:Cc:To:Subject:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=p49DZ11I+/u/UHHcu5yTFpiRBHuzUy75Pad6Ur8MpmA=; b=2PbNEF0WEEUcIHzlm79pXzRXi2 PoWSlNU4Q7SBUDuq8oVHhCOI2IXTPkowpBmyJMgaNHGYmezO9DkS/Fz60XNib2hWT3CSiqk8XjmWh kCRolfUBCZ7fIaAYbZpsG1igL2Rzcho/nFknf5ltSBMQapa1+Y9LLm5+HSbVLpUSzthE2ehEtKa2c pv4ZSwR+6ZAeg7QQTXRDfXdhEmUuG0Z2/PcQ4qbMwRdHkbAg3ay+Kl8jjdGoXMYQnIs2OyuP6QQZl 3CcQSvgAD5MKqDE6fIf8g9m/bUWriM45KhaWMOiYGQ9QmHBxtx7QxQisNRpvof0HduEhHFxLiZoIM 1f6GMOoQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n9exf-00HMla-Ti; Tue, 18 Jan 2022 03:15:09 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n9eSG-00H4NZ-Al for linux-arm-kernel@lists.infradead.org; Tue, 18 Jan 2022 02:42:42 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B9E5A6D; Mon, 17 Jan 2022 18:42:38 -0800 (PST) Received: from [10.163.73.43] (unknown [10.163.73.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A4D1C3F774; Mon, 17 Jan 2022 18:42:36 -0800 (PST) Subject: Re: [bootwrapper PATCH] aarch64: Enable BRBE for the non-secure world To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, andre.przywara@arm.com, robin.murphy@arm.com References: <1642066868-23151-1-git-send-email-anshuman.khandual@arm.com> <20220117132541.GD87485@C02TD0UTHF1T.local> From: Anshuman Khandual Message-ID: Date: Tue, 18 Jan 2022 08:12:39 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20220117132541.GD87485@C02TD0UTHF1T.local> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220117_184240_542008_B66F1D70 X-CRM114-Status: GOOD ( 23.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 1/17/22 6:55 PM, Mark Rutland wrote: > On Mon, Jan 17, 2022 at 04:06:44PM +0530, Anshuman Khandual wrote: >> On 1/13/22 3:54 PM, Mark Rutland wrote: >>> Hi Anshuman, >>> >>> This looks fine structurally, I'm just not sure of a couple of details because >>> I can't find the relevant documentation -- more on that below. >>> >>> On Thu, Jan 13, 2022 at 03:11:08PM +0530, Anshuman Khandual wrote: >>>> MDCR_EL3.SBRBE resets to an UNKNOWN value. Configure it to allow the BRBE >>>> buffer usage and direct register access in the non-secure world. But just >>>> before that, check AA64DFR0_EL1.BRBE and make sure BRBE is implemented. We >>>> still continue to reset MDCR_EL3 register to zero with the exception of >>>> MDCR_EL3.NSPB, MDCR_EL3.NSTB and MDCR_EL3.SBRBE. >>> >>> I'm struggling to find where the BRBE system register fields are documented. >>> >>> I looked at the latest ARM ARM (DDI 0487G.b): >>> >>> https://developer.arm.com/documentation/ddi0487/gb/ >>> >>> ... and the Armv9 supplement (DDI 0608A.a): >>> >>> https://developer.arm.com/documentation/ddi0608/aa/ >>> >>> ... but AFAICT, neither of those describe the bit-positions of the relevant >>> fields, so I can't check that those are correct. The other extensions (at leat >>> TME) describe that in the supplement, so this looks like a bug/oversight. >>> >>> Am I looking at the right documents? If this is meant to be in the supplement, >>> could you please raise a bug report to get that fixed? >> >> Please find the MDCR_EL3.SBRBE definition here. >> >> https://developer.arm.com/documentation/ddi0601/2021-12/AArch64-Registers/ >> MDCR-EL3--Monitor-Debug-Configuration-Register--EL3-?lang=en#fieldset_0-33_32-1 >> >>> >>>> >>>> Signed-off-by: Anshuman Khandual >>>> --- >>>> arch/aarch64/boot.S | 8 ++++++++ >>>> 1 file changed, 8 insertions(+) >>>> >>>> diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S >>>> index bfbb6ec..ca1b292 100644 >>>> --- a/arch/aarch64/boot.S >>>> +++ b/arch/aarch64/boot.S >>>> @@ -103,6 +103,14 @@ ASM_FUNC(_start) >>>> ldr x1, =(0x3 << 24) >>>> orr x0, x0, x1 >>>> >>>> +1: mrs x1, id_aa64dfr0_el1 >>>> + ubfx x1, x1, #52, #4 >>>> + cbz x1, 1f >>>> + >>>> + // Enable BRBE for the non-secure world. >>>> + ldr x1, =(0x3 << 32) >>>> + orr x0, x0, x1 >>>> + >>> >>> I assume this is the `SBRBE` field, which naming-wise sounds like it controls >>> Secure rather than Non-Secure (e,g. by way of comparison to `NSPB`). Is that >> >> Right, that is some what counter-intuitive. >> >>> correct? What effect does the value 0x3 have? >> >> As per the definition above. >> >> 0b11 This control does not cause any direct accesses to BRBE registers or >> instruction to be trapped, and does not cause any Exception levels to >> be a prohibited region. >> >> This basically allows BRBE usage in EL2/EL1. > > Thanks for this! > > Just to check, my understanding, there's nothing else that we need to > initialize to ensure that BRBE won't start recording unexpectedly > out-of-reset, becuase in BRBCR_EL* the E*BRE bits all warm-reset to 0 > and hence prevent recording in any of EL0/EL1/EL2 (and BRBE never > records at EL3). Is that right? Right, that is my understanding as well. Those required bits that start BRBE recording, always warm-reset to 0. > > Assuming so, I'll take this as-is. > > Thanks, > Mark. > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel