* [PATCH v8 0/5] Enable Display for J784S4 and AM69-SK platform
@ 2023-08-01 7:00 Jayesh Choudhary
2023-08-01 7:00 ` [PATCH v8 1/5] arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux Jayesh Choudhary
` (4 more replies)
0 siblings, 5 replies; 14+ messages in thread
From: Jayesh Choudhary @ 2023-08-01 7:00 UTC (permalink / raw)
To: nm, vigneshr
Cc: s-vadapalli, afd, kristo, robh+dt, krzysztof.kozlowski+dt,
conor+dt, rogerq, a-bhatia1, r-ravikumar, sabiya.d, devicetree,
linux-kernel, linux-arm-kernel, j-choudhary
This series adds support for:
- DisplayPort for J784S4-EVM
- Displayport and HDMI for AM69-SK platform
Changelog v7->v8:
- rebase on tag next-20230731
- add AM69 display support
- fix commit heading for patch [2/5]
Changelog v6->v7:
- change compatible for scm_conf to 'simple-bus'
- drop main_cpsw node due to driver dependency on [2]
Changelog v5->v6:
- Change header file according to [1].
- Add idle-state property in serdes_ln_ctrl node.
- Fix dtbs_check warning due to clock-frequency property in serdes_refclk
node by disabling the node in main.dtsi and enabling it in board file
when the clock-frequency node is actually added.
Changelog v4->v5:
- rebased the patches on linux-next tip.
Changelog v3->v4:
- add reg property to serdes_ln_ctrl and fix the node name again to
get rid of dtbs_check error.
- reorder reg, reg-names and ranges property for main_cpsw1.
- correct the order for clocks in serdes_wiz nodes to fix dtbs_check
warnings.
- fix indentation in reg, reg-names and clock property for dss node.
- add comments for the reg type in dss registers.
Changelog v3->v2:
- fix dtc warnings for 'scm_conf' and 'serdes_ln_ctrl' nodes
(Checked all the changes of the series with W=12 option during build)
- added clock-frequency for serdes_refclk along with other EVM changes
This refclk is being used by all the instances of serdes_wiz which
are disabled by default. So configuring refclk when the serdes nodes
are used for the first time is okay.
Changelog v1->v2:
- Moved J784S4 EVM changes together to the last patch
(Suggested by Andrew)
v7 patch link:
<https://lore.kernel.org/all/20230728050859.7370-1-j-choudhary@ti.com/>
[1]: <https://lore.kernel.org/all/20230721125732.122421-1-j-choudhary@ti.com/>
[2]: <https://lore.kernel.org/all/20230605154153.24025-1-afd@ti.com/>
Dasnavis Sabiya (1):
arm64: dts: ti: k3-am69-sk: Add DP and HDMI support
Rahul T R (2):
arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node
arm64: dts: ti: k3-j784s4-evm: Enable DisplayPort-0
Siddharth Vadapalli (2):
arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane
mux
arm64: dts: ti: k3-j784s4-main: Add WIZ and SERDES PHY nodes
arch/arm64/boot/dts/ti/k3-am69-sk.dts | 237 +++++++++++++++++
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 117 +++++++++
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 285 +++++++++++++++++++++
3 files changed, 639 insertions(+)
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v8 1/5] arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux
2023-08-01 7:00 [PATCH v8 0/5] Enable Display for J784S4 and AM69-SK platform Jayesh Choudhary
@ 2023-08-01 7:00 ` Jayesh Choudhary
2023-08-01 14:19 ` Andrew Davis
2023-08-01 7:00 ` [PATCH v8 2/5] arm64: dts: ti: k3-j784s4-main: Add WIZ and SERDES PHY nodes Jayesh Choudhary
` (3 subsequent siblings)
4 siblings, 1 reply; 14+ messages in thread
From: Jayesh Choudhary @ 2023-08-01 7:00 UTC (permalink / raw)
To: nm, vigneshr
Cc: s-vadapalli, afd, kristo, robh+dt, krzysztof.kozlowski+dt,
conor+dt, rogerq, a-bhatia1, r-ravikumar, sabiya.d, devicetree,
linux-kernel, linux-arm-kernel, j-choudhary
From: Siddharth Vadapalli <s-vadapalli@ti.com>
The system controller node manages the CTRL_MMR0 region.
Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
[j-choudhary@ti.com: Fix serdes_ln_ctrl node]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
---
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 40 ++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 11f163e5cadf..8a816563706b 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -5,6 +5,10 @@
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include <dt-bindings/mux/mux.h>
+
+#include "k3-serdes.h"
+
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
@@ -26,6 +30,42 @@ l3cache-sram@200000 {
};
};
+ scm_conf: bus@100000 {
+ compatible = "simple-bus";
+ reg = <0x00 0x00100000 0x00 0x1c000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0x00100000 0x1c000>;
+
+ serdes_ln_ctrl: mux-controller@4080 {
+ compatible = "mmio-mux";
+ reg = <0x00004080 0x30>;
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
+ <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */
+ <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
+ <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */
+ <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
+ <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */
+ idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>,
+ <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
+ <J784S4_SERDES0_LANE2_IP3_UNUSED>,
+ <J784S4_SERDES0_LANE3_USB>,
+ <J784S4_SERDES1_LANE0_PCIE0_LANE0>,
+ <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
+ <J784S4_SERDES1_LANE2_PCIE0_LANE2>,
+ <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
+ <J784S4_SERDES2_LANE0_IP2_UNUSED>,
+ <J784S4_SERDES2_LANE1_IP2_UNUSED>,
+ <J784S4_SERDES2_LANE2_QSGMII_LANE1>,
+ <J784S4_SERDES2_LANE3_QSGMII_LANE2>,
+ <J784S4_SERDES4_LANE0_EDP_LANE0>,
+ <J784S4_SERDES4_LANE1_EDP_LANE1>,
+ <J784S4_SERDES4_LANE2_EDP_LANE2>,
+ <J784S4_SERDES4_LANE3_EDP_LANE3>;
+ };
+ };
+
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v8 2/5] arm64: dts: ti: k3-j784s4-main: Add WIZ and SERDES PHY nodes
2023-08-01 7:00 [PATCH v8 0/5] Enable Display for J784S4 and AM69-SK platform Jayesh Choudhary
2023-08-01 7:00 ` [PATCH v8 1/5] arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux Jayesh Choudhary
@ 2023-08-01 7:00 ` Jayesh Choudhary
2023-08-01 16:56 ` Roger Quadros
2023-08-01 7:00 ` [PATCH v8 3/5] arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node Jayesh Choudhary
` (2 subsequent siblings)
4 siblings, 1 reply; 14+ messages in thread
From: Jayesh Choudhary @ 2023-08-01 7:00 UTC (permalink / raw)
To: nm, vigneshr
Cc: s-vadapalli, afd, kristo, robh+dt, krzysztof.kozlowski+dt,
conor+dt, rogerq, a-bhatia1, r-ravikumar, sabiya.d, devicetree,
linux-kernel, linux-arm-kernel, j-choudhary
From: Siddharth Vadapalli <s-vadapalli@ti.com>
J784S4 SoC has 4 Serdes instances along with their respective WIZ
instances. Add device-tree nodes for them and disable them by default.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
[j-choudhary@ti.com: fix serdes_wiz clock order & disable serdes refclk]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
---
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 172 +++++++++++++++++++++
1 file changed, 172 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 8a816563706b..fbf5ab94d785 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -6,9 +6,19 @@
*/
#include <dt-bindings/mux/mux.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/phy/phy-ti.h>
#include "k3-serdes.h"
+/ {
+ serdes_refclk: serdes-refclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ status = "disabled";
+ };
+};
+
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
@@ -709,6 +719,168 @@ main_sdhci1: mmc@4fb0000 {
status = "disabled";
};
+ serdes_wiz0: wiz@5060000 {
+ compatible = "ti,j784s4-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 404 2>, <&k3_clks 404 6>, <&serdes_refclk>, <&k3_clks 404 5>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
+ assigned-clocks = <&k3_clks 404 6>;
+ assigned-clock-parents = <&k3_clks 404 10>;
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ ranges = <0x5060000 0x00 0x5060000 0x10000>;
+
+ status = "disabled";
+
+ serdes0: serdes@5060000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x05060000 0x010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz0 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 404 6>,
+ <&k3_clks 404 6>,
+ <&k3_clks 404 6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ status = "disabled";
+ };
+ };
+
+ serdes_wiz1: wiz@5070000 {
+ compatible = "ti,j784s4-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 405 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 405 2>, <&k3_clks 405 6>, <&serdes_refclk>, <&k3_clks 405 5>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
+ assigned-clocks = <&k3_clks 405 6>;
+ assigned-clock-parents = <&k3_clks 405 10>;
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ ranges = <0x05070000 0x00 0x05070000 0x10000>;
+
+ status = "disabled";
+
+ serdes1: serdes@5070000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x05070000 0x010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz1 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 405 6>,
+ <&k3_clks 405 6>,
+ <&k3_clks 405 6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ status = "disabled";
+ };
+ };
+
+ serdes_wiz2: wiz@5020000 {
+ compatible = "ti,j784s4-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 406 2>, <&k3_clks 406 6>, <&serdes_refclk>, <&k3_clks 406 5>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
+ assigned-clocks = <&k3_clks 406 6>;
+ assigned-clock-parents = <&k3_clks 406 10>;
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ ranges = <0x05020000 0x00 0x05020000 0x10000>;
+
+ status = "disabled";
+
+ serdes2: serdes@5020000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x05020000 0x010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz2 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz2 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 406 6>,
+ <&k3_clks 406 6>,
+ <&k3_clks 406 6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ status = "disabled";
+ };
+ };
+
+ serdes_wiz4: wiz@5050000 {
+ compatible = "ti,j784s4-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 407 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 407 2>, <&k3_clks 407 6>, <&serdes_refclk>, <&k3_clks 407 5>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
+ assigned-clocks = <&k3_clks 407 6>;
+ assigned-clock-parents = <&k3_clks 407 10>;
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ ranges = <0x05050000 0x00 0x05050000 0x10000>,
+ <0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */
+
+ status = "disabled";
+
+ serdes4: serdes@5050000 {
+ /*
+ * Note: we also map DPTX PHY registers as the Torrent
+ * needs to manage those.
+ */
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x05050000 0x010000>,
+ <0x0a030a00 0x40>; /* DPTX PHY */
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz4 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz4 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 407 6>,
+ <&k3_clks 407 6>,
+ <&k3_clks 407 6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ status = "disabled";
+ };
+ };
+
main_navss: bus@30000000 {
compatible = "simple-bus";
#address-cells = <2>;
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v8 3/5] arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node
2023-08-01 7:00 [PATCH v8 0/5] Enable Display for J784S4 and AM69-SK platform Jayesh Choudhary
2023-08-01 7:00 ` [PATCH v8 1/5] arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux Jayesh Choudhary
2023-08-01 7:00 ` [PATCH v8 2/5] arm64: dts: ti: k3-j784s4-main: Add WIZ and SERDES PHY nodes Jayesh Choudhary
@ 2023-08-01 7:00 ` Jayesh Choudhary
2023-08-01 16:50 ` Roger Quadros
2023-08-01 7:00 ` [PATCH v8 4/5] arm64: dts: ti: k3-j784s4-evm: Enable DisplayPort-0 Jayesh Choudhary
2023-08-01 7:00 ` [PATCH v8 5/5] arm64: dts: ti: k3-am69-sk: Add DP and HDMI support Jayesh Choudhary
4 siblings, 1 reply; 14+ messages in thread
From: Jayesh Choudhary @ 2023-08-01 7:00 UTC (permalink / raw)
To: nm, vigneshr
Cc: s-vadapalli, afd, kristo, robh+dt, krzysztof.kozlowski+dt,
conor+dt, rogerq, a-bhatia1, r-ravikumar, sabiya.d, devicetree,
linux-kernel, linux-arm-kernel, j-choudhary
From: Rahul T R <r-ravikumar@ti.com>
Add DSS and DP-bridge node for J784S4 SoC. DSS IP in J784S4 is
same as DSS IP in J721E, so same compatible is being used.
The DP is Cadence MHDP8546.
Signed-off-by: Rahul T R <r-ravikumar@ti.com>
[j-choudhary@ti.com: move dss & mhdp node together in main, fix dss node]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
---
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 73 ++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index fbf5ab94d785..975661948755 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -1749,4 +1749,77 @@ c71_3: dsp@67800000 {
resets = <&k3_reset 40 1>;
firmware-name = "j784s4-c71_3-fw";
};
+
+ mhdp: dp-bridge@a000000 {
+ compatible = "ti,j721e-mhdp8546";
+
+ reg = <0x0 0xa000000 0x0 0x30a00>,
+ <0x0 0x4f40000 0x0 0x20>;
+ reg-names = "mhdptx", "j721e-intg";
+
+ clocks = <&k3_clks 217 11>;
+
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
+
+ power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
+
+ status = "disabled";
+
+ dp0_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ dss: dss@4a00000 {
+ compatible = "ti,j721e-dss";
+ reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */
+ <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
+ <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
+ <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
+ <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
+ <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
+ <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
+ <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
+ <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
+ <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
+ <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
+ <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
+ <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
+ <0x00 0x04aa0000 0x00 0x10000>, /* vp1 */
+ <0x00 0x04ac0000 0x00 0x10000>, /* vp1 */
+ <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
+ <0x00 0x04af0000 0x00 0x10000>; /* wb */
+
+ reg-names = "common_m", "common_s0",
+ "common_s1", "common_s2",
+ "vidl1", "vidl2","vid1","vid2",
+ "ovr1", "ovr2", "ovr3", "ovr4",
+ "vp1", "vp2", "vp3", "vp4",
+ "wb";
+
+ clocks = <&k3_clks 218 0>,
+ <&k3_clks 218 2>,
+ <&k3_clks 218 5>,
+ <&k3_clks 218 14>,
+ <&k3_clks 218 18>;
+ clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
+
+ power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
+
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common_m",
+ "common_s0",
+ "common_s1",
+ "common_s2";
+
+ status = "disabled";
+
+ dss_ports: ports {
+ };
+ };
};
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v8 4/5] arm64: dts: ti: k3-j784s4-evm: Enable DisplayPort-0
2023-08-01 7:00 [PATCH v8 0/5] Enable Display for J784S4 and AM69-SK platform Jayesh Choudhary
` (2 preceding siblings ...)
2023-08-01 7:00 ` [PATCH v8 3/5] arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node Jayesh Choudhary
@ 2023-08-01 7:00 ` Jayesh Choudhary
2023-08-01 16:40 ` Roger Quadros
2023-08-01 7:00 ` [PATCH v8 5/5] arm64: dts: ti: k3-am69-sk: Add DP and HDMI support Jayesh Choudhary
4 siblings, 1 reply; 14+ messages in thread
From: Jayesh Choudhary @ 2023-08-01 7:00 UTC (permalink / raw)
To: nm, vigneshr
Cc: s-vadapalli, afd, kristo, robh+dt, krzysztof.kozlowski+dt,
conor+dt, rogerq, a-bhatia1, r-ravikumar, sabiya.d, devicetree,
linux-kernel, linux-arm-kernel, j-choudhary
From: Rahul T R <r-ravikumar@ti.com>
Enable display for J784S4 EVM.
Add assigned clocks for DSS, DT node for DisplayPort PHY and pinmux for
DP HPD. Add the clock frequency for serdes_refclk.
Add the endpoint nodes to describe connection from:
DSS => MHDP => DisplayPort connector.
Also add the GPIO expander-4 node and pinmux for main_i2c4 which is
required for controlling DP power. Set status for all required nodes
for DP-0 as "okay".
Signed-off-by: Rahul T R <r-ravikumar@ti.com>
[j-choudhary@ti.com: move all the changes together to enable DP-0 in EVM]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
---
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 117 +++++++++++++++++++++++
1 file changed, 117 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index 7ad152a1b90f..1145a7f046e2 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -249,6 +249,28 @@ vdd_sd_dv: regulator-TLV71033 {
states = <1800000 0x0>,
<3300000 0x1>;
};
+
+ dp0_pwr_3v3: regulator-dp0-prw {
+ compatible = "regulator-fixed";
+ regulator-name = "dp0-pwr";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&exp4 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ dp0: dp0-connector {
+ compatible = "dp-connector";
+ label = "DP0";
+ type = "full-size";
+ dp-pwr-supply = <&dp0_pwr_3v3>;
+
+ port {
+ dp0_connector_in: endpoint {
+ remote-endpoint = <&dp0_out>;
+ };
+ };
+ };
};
&main_pmx0 {
@@ -286,6 +308,19 @@ vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */
>;
};
+
+ dp0_pins_default: dp0-pins-default {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */
+ >;
+ };
+
+ main_i2c4_pins_default: main-i2c4-pins-default {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */
+ J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */
+ >;
+ };
};
&wkup_pmx2 {
@@ -827,3 +862,85 @@ adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
};
+
+&serdes_refclk {
+ status = "okay";
+ clock-frequency = <100000000>;
+};
+
+&dss {
+ status = "okay";
+ assigned-clocks = <&k3_clks 218 2>,
+ <&k3_clks 218 5>,
+ <&k3_clks 218 14>,
+ <&k3_clks 218 18>;
+ assigned-clock-parents = <&k3_clks 218 3>,
+ <&k3_clks 218 7>,
+ <&k3_clks 218 16>,
+ <&k3_clks 218 22>;
+};
+
+&serdes_wiz4 {
+ status = "okay";
+};
+
+&serdes4 {
+ status = "okay";
+ serdes4_dp_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <4>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_DP>;
+ resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>,
+ <&serdes_wiz4 3>, <&serdes_wiz4 4>;
+ };
+};
+
+&mhdp {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dp0_pins_default>;
+ phys = <&serdes4_dp_link>;
+ phy-names = "dpphy";
+};
+
+&dss_ports {
+ port {
+ dpi0_out: endpoint {
+ remote-endpoint = <&dp0_in>;
+ };
+ };
+};
+
+&main_i2c4 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c4_pins_default>;
+ clock-frequency = <400000>;
+
+ exp4: gpio@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&dp0_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dp0_in: endpoint {
+ remote-endpoint = <&dpi0_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ dp0_out: endpoint {
+ remote-endpoint = <&dp0_connector_in>;
+ };
+ };
+};
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v8 5/5] arm64: dts: ti: k3-am69-sk: Add DP and HDMI support
2023-08-01 7:00 [PATCH v8 0/5] Enable Display for J784S4 and AM69-SK platform Jayesh Choudhary
` (3 preceding siblings ...)
2023-08-01 7:00 ` [PATCH v8 4/5] arm64: dts: ti: k3-j784s4-evm: Enable DisplayPort-0 Jayesh Choudhary
@ 2023-08-01 7:00 ` Jayesh Choudhary
2023-08-01 16:48 ` Roger Quadros
4 siblings, 1 reply; 14+ messages in thread
From: Jayesh Choudhary @ 2023-08-01 7:00 UTC (permalink / raw)
To: nm, vigneshr
Cc: s-vadapalli, afd, kristo, robh+dt, krzysztof.kozlowski+dt,
conor+dt, rogerq, a-bhatia1, r-ravikumar, sabiya.d, devicetree,
linux-kernel, linux-arm-kernel, j-choudhary
From: Dasnavis Sabiya <sabiya.d@ti.com>
AM69 starter kit features an HDMI port and an eDP port.
Add assigned clocks for DSS, DT node for DisplayPort PHY,
pinmux for HDMI hotplug and power down, mcu_i2c1 and dss_vout
for HDMI.
Also enable Serdes4 settings for DP display.
Add the endpoint nodes to describe connection from:
DSS => MHDP => DisplayPort connector
DSS => TI TFP410 DPI-to-DVI Bridge => HDMI connector
Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com>
[j-choudhary@ti.com: Fix dvi-bridge, dss, mhdp and serdes-refclk]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
---
arch/arm64/boot/dts/ti/k3-am69-sk.dts | 237 ++++++++++++++++++++++++++
1 file changed, 237 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts
index d282c2c633c1..d9a0794bcf6e 100644
--- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts
@@ -107,6 +107,83 @@ vdd_sd_dv: regulator-tlv71033 {
states = <1800000 0x0>,
<3300000 0x1>;
};
+
+ dp0_pwr_3v3: regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "dp0-pwr";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dp_pwr_en_pins_default>;
+ gpio = <&main_gpio0 4 0>; /* DP0_3V3 _EN */
+ enable-active-high;
+ };
+
+ dp0: connector {
+ compatible = "dp-connector";
+ label = "DP0";
+ type = "full-size";
+ dp-pwr-supply = <&dp0_pwr_3v3>;
+
+ port {
+ dp0_connector_in: endpoint {
+ remote-endpoint = <&dp0_out>;
+ };
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "a";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_hpd_pins_default>;
+
+ ddc-i2c-bus = <&mcu_i2c1>;
+
+ /* HDMI_HPD */
+ hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>;
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&tfp410_out>;
+ };
+ };
+ };
+
+ dvi-bridge {
+ compatible = "ti,tfp410";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pdn_pins_default>;
+
+ /* HDMI_PDn */
+ powerdown-gpios = <&wkup_gpio0 14 GPIO_ACTIVE_LOW>;
+ ti,deskew = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tfp410_in: endpoint {
+ remote-endpoint = <&dpi1_out0>;
+ pclk-sample = <1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tfp410_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
};
&main_pmx0 {
@@ -161,6 +238,57 @@ J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.GPIO0_2 */
J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */
>;
};
+
+ dp0_pins_default: dp0-pins-default {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x014, PIN_INPUT, 13) /* (AG33) MCAN14_TX.DP0_HPD */
+ >;
+ };
+
+ dp_pwr_en_pins_default: dp-pwr-en-pins-default {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x010, PIN_INPUT, 7) /* (AH33) MCAN13_RX.GPIO0_4 */
+ >;
+ };
+
+ dss_vout0_pins_default: dss-vout0-pins-default {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x074, PIN_OUTPUT, 2) /* (AC33) MCAN2_TX.VOUT0_DATA0 */
+ J784S4_IOPAD(0x070, PIN_OUTPUT, 2) /* (AH38) MCAN1_RX.VOUT0_DATA1 */
+ J784S4_IOPAD(0x07c, PIN_OUTPUT, 2) /* (AJ38) MCASP0_AXR3.VOUT0_DATA2 */
+ J784S4_IOPAD(0x068, PIN_OUTPUT, 2) /* (AE38) MCAN0_RX.VOUT0_DATA3 */
+ J784S4_IOPAD(0x064, PIN_OUTPUT, 2) /* (AF38) MCAN0_TX.VOUT0_DATA4 */
+ J784S4_IOPAD(0x060, PIN_OUTPUT, 2) /* (AE36) MCASP2_AXR1.VOUT0_DATA5 */
+ J784S4_IOPAD(0x05c, PIN_OUTPUT, 2) /* (AC36) MCASP2_AXR0.VOUT0_DATA6 */
+ J784S4_IOPAD(0x058, PIN_OUTPUT, 2) /* (AE37) MCASP2_AFSX.VOUT0_DATA7 */
+ J784S4_IOPAD(0x054, PIN_OUTPUT, 2) /* (AD37) MCASP2_ACLKX.VOUT0_DATA8 */
+ J784S4_IOPAD(0x050, PIN_OUTPUT, 2) /* (AC37) MCASP1_AXR2.VOUT0_DATA9 */
+ J784S4_IOPAD(0x04c, PIN_OUTPUT, 2) /* (AC32) MCASP1_AXR1.VOUT0_DATA10 */
+ J784S4_IOPAD(0x048, PIN_OUTPUT, 2) /* (AK33) MCASP0_AXR2.VOUT0_DATA11 */
+ J784S4_IOPAD(0x044, PIN_OUTPUT, 2) /* (AG37) MCASP0_AXR1.VOUT0_DATA12 */
+ J784S4_IOPAD(0x040, PIN_OUTPUT, 2) /* (AF37) MCASP0_AXR0.VOUT0_DATA13 */
+ J784S4_IOPAD(0x03c, PIN_OUTPUT, 2) /* (AK38) MCASP0_AFSX.VOUT0_DATA14 */
+ J784S4_IOPAD(0x038, PIN_OUTPUT, 2) /* (AK35) MCASP0_ACLKX.VOUT0_DATA15 */
+ J784S4_IOPAD(0x0c8, PIN_OUTPUT, 2) /* (AJ32) EXT_REFCLK1.VOUT0_DATA16 */
+ J784S4_IOPAD(0x030, PIN_OUTPUT, 2) /* (AK37) GPIO0_12.VOUT0_DATA17 */
+ J784S4_IOPAD(0x02c, PIN_OUTPUT, 2) /* (AL32) GPIO0_11.VOUT0_DATA18 */
+ J784S4_IOPAD(0x028, PIN_OUTPUT, 2) /* (AE33) MCAN16_RX.VOUT0_DATA19 */
+ J784S4_IOPAD(0x024, PIN_OUTPUT, 2) /* (AH34) MCAN16_TX.VOUT0_DATA20 */
+ J784S4_IOPAD(0x020, PIN_OUTPUT, 2) /* (AJ35) MCAN15_RX.VOUT0_DATA21 */
+ J784S4_IOPAD(0x01c, PIN_OUTPUT, 2) /* (AG34) MCAN15_TX.VOUT0_DATA22 */
+ J784S4_IOPAD(0x018, PIN_OUTPUT, 2) /* (AK36) MCAN14_RX.VOUT0_DATA23 */
+ J784S4_IOPAD(0x084, PIN_OUTPUT, 2) /* (AG38) MCASP0_AXR5.VOUT0_DE */
+ J784S4_IOPAD(0x080, PIN_OUTPUT, 2) /* (AK34) MCASP0_AXR4.VOUT0_HSYNC */
+ J784S4_IOPAD(0x078, PIN_OUTPUT, 2) /* (AH37) MCAN2_RX.VOUT0_PCLK */
+ J784S4_IOPAD(0x088, PIN_OUTPUT, 2) /* (AF36) MCASP0_AXR6.VOUT0_VSYNC */
+ >;
+ };
+
+ hdmi_hpd_pins_default: hdmi-hpd-pins-default {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x000, PIN_INPUT, 7) /* (AN35) EXTINTN.GPIO0_0 */
+ >;
+ };
};
&wkup_pmx2 {
@@ -231,6 +359,21 @@ J784S4_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (J36) WKUP_GPIO0_3 */
J784S4_WKUP_IOPAD(0x11c, PIN_INPUT, 7) /* (M34) WKUP_GPIO0_67 */
>;
};
+
+ mcu_i2c1_pins_default: mcu-i2c1-pins-default {
+ pinctrl-single,pins = <
+ /* (L35) WKUP_GPIO0_8.MCU_I2C1_SCL */
+ J784S4_WKUP_IOPAD(0x078, PIN_INPUT_PULLUP, 0)
+ /* (L34) WKUP_GPIO0_9.MCU_I2C1_SDA */
+ J784S4_WKUP_IOPAD(0x07c, PIN_INPUT_PULLUP, 0)
+ >;
+ };
+
+ hdmi_pdn_pins_default: hdmi-pdn-pins-default {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 7) /* (H37) WKUP_GPIO0_14 */
+ >;
+ };
};
&wkup_pmx3 {
@@ -350,3 +493,97 @@ &mcu_cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&mcu_phy0>;
};
+
+&wkup_gpio_intr {
+ status = "okay";
+};
+
+&mcu_i2c1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_i2c1_pins_default>;
+ clock-frequency = <100000>;
+};
+
+&serdes_refclk {
+ status = "okay";
+ clock-frequency = <100000000>;
+};
+
+&dss {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dss_vout0_pins_default>;
+ assigned-clocks = <&k3_clks 218 2>,
+ <&k3_clks 218 5>,
+ <&k3_clks 218 14>,
+ <&k3_clks 218 18>;
+ assigned-clock-parents = <&k3_clks 218 3>,
+ <&k3_clks 218 7>,
+ <&k3_clks 218 16>,
+ <&k3_clks 218 22>;
+};
+
+&serdes_wiz4 {
+ status = "okay";
+};
+
+&serdes4 {
+ status = "okay";
+ serdes4_dp_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <4>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_DP>;
+ resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>,
+ <&serdes_wiz4 3>, <&serdes_wiz4 4>;
+ };
+};
+
+&mhdp {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dp0_pins_default>;
+ phys = <&serdes4_dp_link>;
+ phy-names = "dpphy";
+};
+
+&dss_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* DP */
+ port@0 {
+ reg = <0>;
+ dpi0_out: endpoint {
+ remote-endpoint = <&dp0_in>;
+ };
+ };
+
+ /* HDMI */
+ port@1 {
+ reg = <1>;
+ dpi1_out0: endpoint {
+ remote-endpoint = <&tfp410_in>;
+ };
+ };
+};
+
+&dp0_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dp0_in: endpoint {
+ remote-endpoint = <&dpi0_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ dp0_out: endpoint {
+ remote-endpoint = <&dp0_connector_in>;
+ };
+ };
+};
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v8 1/5] arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux
2023-08-01 7:00 ` [PATCH v8 1/5] arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux Jayesh Choudhary
@ 2023-08-01 14:19 ` Andrew Davis
0 siblings, 0 replies; 14+ messages in thread
From: Andrew Davis @ 2023-08-01 14:19 UTC (permalink / raw)
To: Jayesh Choudhary, nm, vigneshr
Cc: s-vadapalli, kristo, robh+dt, krzysztof.kozlowski+dt, conor+dt,
rogerq, a-bhatia1, r-ravikumar, sabiya.d, devicetree,
linux-kernel, linux-arm-kernel
On 8/1/23 2:00 AM, Jayesh Choudhary wrote:
> From: Siddharth Vadapalli <s-vadapalli@ti.com>
>
> The system controller node manages the CTRL_MMR0 region.
> Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux.
>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> [j-choudhary@ti.com: Fix serdes_ln_ctrl node]
> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
> ---
> arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 40 ++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> index 11f163e5cadf..8a816563706b 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> @@ -5,6 +5,10 @@
> * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
> */
>
> +#include <dt-bindings/mux/mux.h>
> +
> +#include "k3-serdes.h"
> +
> &cbass_main {
> msmc_ram: sram@70000000 {
> compatible = "mmio-sram";
> @@ -26,6 +30,42 @@ l3cache-sram@200000 {
> };
> };
>
> + scm_conf: bus@100000 {
> + compatible = "simple-bus";
> + reg = <0x00 0x00100000 0x00 0x1c000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x00 0x00 0x00100000 0x1c000>;
> +
> + serdes_ln_ctrl: mux-controller@4080 {
> + compatible = "mmio-mux";
The parent is not a syscon node, this should be "reg-mux".
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/mux/reg-mux.yaml#n19
Andrew
> + reg = <0x00004080 0x30>;
> + #mux-control-cells = <1>;
> + mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
> + <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */
> + <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
> + <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */
> + <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
> + <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */
> + idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>,
> + <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
> + <J784S4_SERDES0_LANE2_IP3_UNUSED>,
> + <J784S4_SERDES0_LANE3_USB>,
> + <J784S4_SERDES1_LANE0_PCIE0_LANE0>,
> + <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
> + <J784S4_SERDES1_LANE2_PCIE0_LANE2>,
> + <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
> + <J784S4_SERDES2_LANE0_IP2_UNUSED>,
> + <J784S4_SERDES2_LANE1_IP2_UNUSED>,
> + <J784S4_SERDES2_LANE2_QSGMII_LANE1>,
> + <J784S4_SERDES2_LANE3_QSGMII_LANE2>,
> + <J784S4_SERDES4_LANE0_EDP_LANE0>,
> + <J784S4_SERDES4_LANE1_EDP_LANE1>,
> + <J784S4_SERDES4_LANE2_EDP_LANE2>,
> + <J784S4_SERDES4_LANE3_EDP_LANE3>;
> + };
> + };
> +
> gic500: interrupt-controller@1800000 {
> compatible = "arm,gic-v3";
> #address-cells = <2>;
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v8 4/5] arm64: dts: ti: k3-j784s4-evm: Enable DisplayPort-0
2023-08-01 7:00 ` [PATCH v8 4/5] arm64: dts: ti: k3-j784s4-evm: Enable DisplayPort-0 Jayesh Choudhary
@ 2023-08-01 16:40 ` Roger Quadros
0 siblings, 0 replies; 14+ messages in thread
From: Roger Quadros @ 2023-08-01 16:40 UTC (permalink / raw)
To: Jayesh Choudhary, nm, vigneshr
Cc: s-vadapalli, afd, kristo, robh+dt, krzysztof.kozlowski+dt,
conor+dt, a-bhatia1, r-ravikumar, sabiya.d, devicetree,
linux-kernel, linux-arm-kernel
On 01/08/2023 10:00, Jayesh Choudhary wrote:
> From: Rahul T R <r-ravikumar@ti.com>
>
> Enable display for J784S4 EVM.
>
> Add assigned clocks for DSS, DT node for DisplayPort PHY and pinmux for
> DP HPD. Add the clock frequency for serdes_refclk.
>
> Add the endpoint nodes to describe connection from:
> DSS => MHDP => DisplayPort connector.
>
> Also add the GPIO expander-4 node and pinmux for main_i2c4 which is
> required for controlling DP power. Set status for all required nodes
> for DP-0 as "okay".
>
> Signed-off-by: Rahul T R <r-ravikumar@ti.com>
> [j-choudhary@ti.com: move all the changes together to enable DP-0 in EVM]
> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
> ---
> arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 117 +++++++++++++++++++++++
> 1 file changed, 117 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> index 7ad152a1b90f..1145a7f046e2 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> @@ -249,6 +249,28 @@ vdd_sd_dv: regulator-TLV71033 {
> states = <1800000 0x0>,
> <3300000 0x1>;
> };
> +
> + dp0_pwr_3v3: regulator-dp0-prw {
> + compatible = "regulator-fixed";
> + regulator-name = "dp0-pwr";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&exp4 0 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + dp0: dp0-connector {
dp0-connector is not a standard name.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
how about connector-dp0?
> + compatible = "dp-connector";
> + label = "DP0";
> + type = "full-size";
> + dp-pwr-supply = <&dp0_pwr_3v3>;
> +
> + port {
> + dp0_connector_in: endpoint {
> + remote-endpoint = <&dp0_out>;
> + };
> + };
> + };
> };
>
> &main_pmx0 {
> @@ -286,6 +308,19 @@ vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
> J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */
> >;
> };
> +
> + dp0_pins_default: dp0-pins-default {
> + pinctrl-single,pins = <
> + J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */
> + >;
> + };
> +
> + main_i2c4_pins_default: main-i2c4-pins-default {
> + pinctrl-single,pins = <
> + J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */
> + J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */
> + >;
> + };
> };
>
> &wkup_pmx2 {
> @@ -827,3 +862,85 @@ adc {
> ti,adc-channels = <0 1 2 3 4 5 6 7>;
> };
> };
> +
> +&serdes_refclk {
> + status = "okay";
> + clock-frequency = <100000000>;
> +};
> +
> +&dss {
> + status = "okay";
> + assigned-clocks = <&k3_clks 218 2>,
> + <&k3_clks 218 5>,
> + <&k3_clks 218 14>,
> + <&k3_clks 218 18>;
> + assigned-clock-parents = <&k3_clks 218 3>,
> + <&k3_clks 218 7>,
> + <&k3_clks 218 16>,
> + <&k3_clks 218 22>;
> +};
> +
> +&serdes_wiz4 {
> + status = "okay";
> +};
> +
> +&serdes4 {
> + status = "okay";
> + serdes4_dp_link: phy@0 {
> + reg = <0>;
> + cdns,num-lanes = <4>;
> + #phy-cells = <0>;
> + cdns,phy-type = <PHY_TYPE_DP>;
> + resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>,
> + <&serdes_wiz4 3>, <&serdes_wiz4 4>;
> + };
> +};
> +
> +&mhdp {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&dp0_pins_default>;
> + phys = <&serdes4_dp_link>;
> + phy-names = "dpphy";
> +};
> +
> +&dss_ports {
> + port {
> + dpi0_out: endpoint {
> + remote-endpoint = <&dp0_in>;
> + };
> + };
> +};
> +
> +&main_i2c4 {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_i2c4_pins_default>;
> + clock-frequency = <400000>;
> +
> + exp4: gpio@20 {
> + compatible = "ti,tca6408";
> + reg = <0x20>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +};
> +
> +&dp0_ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dp0_in: endpoint {
> + remote-endpoint = <&dpi0_out>;
> + };
> + };
> +
> + port@4 {
> + reg = <4>;
> + dp0_out: endpoint {
> + remote-endpoint = <&dp0_connector_in>;
> + };
> + };
> +};
--
cheers,
-roger
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v8 5/5] arm64: dts: ti: k3-am69-sk: Add DP and HDMI support
2023-08-01 7:00 ` [PATCH v8 5/5] arm64: dts: ti: k3-am69-sk: Add DP and HDMI support Jayesh Choudhary
@ 2023-08-01 16:48 ` Roger Quadros
2023-08-01 16:58 ` Roger Quadros
0 siblings, 1 reply; 14+ messages in thread
From: Roger Quadros @ 2023-08-01 16:48 UTC (permalink / raw)
To: Jayesh Choudhary, nm, vigneshr, Tomi Valkeinen
Cc: s-vadapalli, afd, kristo, robh+dt, krzysztof.kozlowski+dt,
conor+dt, a-bhatia1, r-ravikumar, sabiya.d, devicetree,
linux-kernel, linux-arm-kernel
On 01/08/2023 10:00, Jayesh Choudhary wrote:
> From: Dasnavis Sabiya <sabiya.d@ti.com>
>
> AM69 starter kit features an HDMI port and an eDP port.
>
> Add assigned clocks for DSS, DT node for DisplayPort PHY,
> pinmux for HDMI hotplug and power down, mcu_i2c1 and dss_vout
> for HDMI.
> Also enable Serdes4 settings for DP display.
>
> Add the endpoint nodes to describe connection from:
> DSS => MHDP => DisplayPort connector
> DSS => TI TFP410 DPI-to-DVI Bridge => HDMI connector
>
> Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com>
> [j-choudhary@ti.com: Fix dvi-bridge, dss, mhdp and serdes-refclk]
> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
> ---
> arch/arm64/boot/dts/ti/k3-am69-sk.dts | 237 ++++++++++++++++++++++++++
> 1 file changed, 237 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts
> index d282c2c633c1..d9a0794bcf6e 100644
> --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts
> @@ -107,6 +107,83 @@ vdd_sd_dv: regulator-tlv71033 {
> states = <1800000 0x0>,
> <3300000 0x1>;
> };
> +
> + dp0_pwr_3v3: regulator {
To be consistent with the rest of the file please
use regulator-dp0-pwr
> + compatible = "regulator-fixed";
> + regulator-name = "dp0-pwr";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&dp_pwr_en_pins_default>;
> + gpio = <&main_gpio0 4 0>; /* DP0_3V3 _EN */
> + enable-active-high;
> + };
> +
> + dp0: connector {
connector-dp0
> + compatible = "dp-connector";
> + label = "DP0";
> + type = "full-size";
> + dp-pwr-supply = <&dp0_pwr_3v3>;
> +
> + port {
> + dp0_connector_in: endpoint {
> + remote-endpoint = <&dp0_out>;
> + };
> + };
> + };
> +
> + hdmi-connector {
connector-hdmi
> + compatible = "hdmi-connector";
> + label = "hdmi";
> + type = "a";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&hdmi_hpd_pins_default>;
> +
> + ddc-i2c-bus = <&mcu_i2c1>;
> +
> + /* HDMI_HPD */
> + hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>;
> +
> + port {
> + hdmi_connector_in: endpoint {
> + remote-endpoint = <&tfp410_out>;
> + };
> + };
> + };
> +
> + dvi-bridge {
Although DT binding doc for ti,tfp410 says encoder
a name starting with bridge maybe more appropriate.
> + compatible = "ti,tfp410";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&hdmi_pdn_pins_default>;
> +
> + /* HDMI_PDn */
> + powerdown-gpios = <&wkup_gpio0 14 GPIO_ACTIVE_LOW>;
> + ti,deskew = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + tfp410_in: endpoint {
> + remote-endpoint = <&dpi1_out0>;
> + pclk-sample = <1>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + tfp410_out: endpoint {
> + remote-endpoint = <&hdmi_connector_in>;
> + };
> + };
> + };
> + };
> };
>
> &main_pmx0 {
> @@ -161,6 +238,57 @@ J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.GPIO0_2 */
> J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */
> >;
> };
> +
> + dp0_pins_default: dp0-pins-default {
> + pinctrl-single,pins = <
> + J784S4_IOPAD(0x014, PIN_INPUT, 13) /* (AG33) MCAN14_TX.DP0_HPD */
> + >;
> + };
> +
> + dp_pwr_en_pins_default: dp-pwr-en-pins-default {
> + pinctrl-single,pins = <
> + J784S4_IOPAD(0x010, PIN_INPUT, 7) /* (AH33) MCAN13_RX.GPIO0_4 */
> + >;
> + };
> +
> + dss_vout0_pins_default: dss-vout0-pins-default {
> + pinctrl-single,pins = <
> + J784S4_IOPAD(0x074, PIN_OUTPUT, 2) /* (AC33) MCAN2_TX.VOUT0_DATA0 */
> + J784S4_IOPAD(0x070, PIN_OUTPUT, 2) /* (AH38) MCAN1_RX.VOUT0_DATA1 */
> + J784S4_IOPAD(0x07c, PIN_OUTPUT, 2) /* (AJ38) MCASP0_AXR3.VOUT0_DATA2 */
> + J784S4_IOPAD(0x068, PIN_OUTPUT, 2) /* (AE38) MCAN0_RX.VOUT0_DATA3 */
> + J784S4_IOPAD(0x064, PIN_OUTPUT, 2) /* (AF38) MCAN0_TX.VOUT0_DATA4 */
> + J784S4_IOPAD(0x060, PIN_OUTPUT, 2) /* (AE36) MCASP2_AXR1.VOUT0_DATA5 */
> + J784S4_IOPAD(0x05c, PIN_OUTPUT, 2) /* (AC36) MCASP2_AXR0.VOUT0_DATA6 */
> + J784S4_IOPAD(0x058, PIN_OUTPUT, 2) /* (AE37) MCASP2_AFSX.VOUT0_DATA7 */
> + J784S4_IOPAD(0x054, PIN_OUTPUT, 2) /* (AD37) MCASP2_ACLKX.VOUT0_DATA8 */
> + J784S4_IOPAD(0x050, PIN_OUTPUT, 2) /* (AC37) MCASP1_AXR2.VOUT0_DATA9 */
> + J784S4_IOPAD(0x04c, PIN_OUTPUT, 2) /* (AC32) MCASP1_AXR1.VOUT0_DATA10 */
> + J784S4_IOPAD(0x048, PIN_OUTPUT, 2) /* (AK33) MCASP0_AXR2.VOUT0_DATA11 */
> + J784S4_IOPAD(0x044, PIN_OUTPUT, 2) /* (AG37) MCASP0_AXR1.VOUT0_DATA12 */
> + J784S4_IOPAD(0x040, PIN_OUTPUT, 2) /* (AF37) MCASP0_AXR0.VOUT0_DATA13 */
> + J784S4_IOPAD(0x03c, PIN_OUTPUT, 2) /* (AK38) MCASP0_AFSX.VOUT0_DATA14 */
> + J784S4_IOPAD(0x038, PIN_OUTPUT, 2) /* (AK35) MCASP0_ACLKX.VOUT0_DATA15 */
> + J784S4_IOPAD(0x0c8, PIN_OUTPUT, 2) /* (AJ32) EXT_REFCLK1.VOUT0_DATA16 */
> + J784S4_IOPAD(0x030, PIN_OUTPUT, 2) /* (AK37) GPIO0_12.VOUT0_DATA17 */
> + J784S4_IOPAD(0x02c, PIN_OUTPUT, 2) /* (AL32) GPIO0_11.VOUT0_DATA18 */
> + J784S4_IOPAD(0x028, PIN_OUTPUT, 2) /* (AE33) MCAN16_RX.VOUT0_DATA19 */
> + J784S4_IOPAD(0x024, PIN_OUTPUT, 2) /* (AH34) MCAN16_TX.VOUT0_DATA20 */
> + J784S4_IOPAD(0x020, PIN_OUTPUT, 2) /* (AJ35) MCAN15_RX.VOUT0_DATA21 */
> + J784S4_IOPAD(0x01c, PIN_OUTPUT, 2) /* (AG34) MCAN15_TX.VOUT0_DATA22 */
> + J784S4_IOPAD(0x018, PIN_OUTPUT, 2) /* (AK36) MCAN14_RX.VOUT0_DATA23 */
> + J784S4_IOPAD(0x084, PIN_OUTPUT, 2) /* (AG38) MCASP0_AXR5.VOUT0_DE */
> + J784S4_IOPAD(0x080, PIN_OUTPUT, 2) /* (AK34) MCASP0_AXR4.VOUT0_HSYNC */
> + J784S4_IOPAD(0x078, PIN_OUTPUT, 2) /* (AH37) MCAN2_RX.VOUT0_PCLK */
> + J784S4_IOPAD(0x088, PIN_OUTPUT, 2) /* (AF36) MCASP0_AXR6.VOUT0_VSYNC */
> + >;
> + };
> +
> + hdmi_hpd_pins_default: hdmi-hpd-pins-default {
> + pinctrl-single,pins = <
> + J784S4_IOPAD(0x000, PIN_INPUT, 7) /* (AN35) EXTINTN.GPIO0_0 */
> + >;
> + };
> };
>
> &wkup_pmx2 {
> @@ -231,6 +359,21 @@ J784S4_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (J36) WKUP_GPIO0_3 */
> J784S4_WKUP_IOPAD(0x11c, PIN_INPUT, 7) /* (M34) WKUP_GPIO0_67 */
> >;
> };
> +
> + mcu_i2c1_pins_default: mcu-i2c1-pins-default {
> + pinctrl-single,pins = <
> + /* (L35) WKUP_GPIO0_8.MCU_I2C1_SCL */
> + J784S4_WKUP_IOPAD(0x078, PIN_INPUT_PULLUP, 0)
> + /* (L34) WKUP_GPIO0_9.MCU_I2C1_SDA */
> + J784S4_WKUP_IOPAD(0x07c, PIN_INPUT_PULLUP, 0)
> + >;
> + };
> +
> + hdmi_pdn_pins_default: hdmi-pdn-pins-default {
> + pinctrl-single,pins = <
> + J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 7) /* (H37) WKUP_GPIO0_14 */
> + >;
> + };
> };
>
> &wkup_pmx3 {
> @@ -350,3 +493,97 @@ &mcu_cpsw_port1 {
> phy-mode = "rgmii-rxid";
> phy-handle = <&mcu_phy0>;
> };
> +
> +&wkup_gpio_intr {
> + status = "okay";
> +};
> +
> +&mcu_i2c1 {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&mcu_i2c1_pins_default>;
> + clock-frequency = <100000>;
> +};
> +
> +&serdes_refclk {
> + status = "okay";
> + clock-frequency = <100000000>;
> +};
> +
> +&dss {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&dss_vout0_pins_default>;
> + assigned-clocks = <&k3_clks 218 2>,
> + <&k3_clks 218 5>,
> + <&k3_clks 218 14>,
> + <&k3_clks 218 18>;
> + assigned-clock-parents = <&k3_clks 218 3>,
> + <&k3_clks 218 7>,
> + <&k3_clks 218 16>,
> + <&k3_clks 218 22>;
> +};
> +
> +&serdes_wiz4 {
> + status = "okay";
> +};
> +
> +&serdes4 {
> + status = "okay";
> + serdes4_dp_link: phy@0 {
> + reg = <0>;
> + cdns,num-lanes = <4>;
> + #phy-cells = <0>;
> + cdns,phy-type = <PHY_TYPE_DP>;
> + resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>,
> + <&serdes_wiz4 3>, <&serdes_wiz4 4>;
> + };
> +};
> +
> +&mhdp {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&dp0_pins_default>;
> + phys = <&serdes4_dp_link>;
> + phy-names = "dpphy";
> +};
> +
> +&dss_ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* DP */
> + port@0 {
> + reg = <0>;
> + dpi0_out: endpoint {
> + remote-endpoint = <&dp0_in>;
> + };
> + };
> +
> + /* HDMI */
> + port@1 {
> + reg = <1>;
> + dpi1_out0: endpoint {
> + remote-endpoint = <&tfp410_in>;
> + };
> + };
> +};
> +
> +&dp0_ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dp0_in: endpoint {
> + remote-endpoint = <&dpi0_out>;
> + };
> + };
> +
> + port@4 {
> + reg = <4>;
> + dp0_out: endpoint {
> + remote-endpoint = <&dp0_connector_in>;
> + };
> + };
> +};
--
cheers,
-roger
_______________________________________________
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v8 3/5] arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node
2023-08-01 7:00 ` [PATCH v8 3/5] arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node Jayesh Choudhary
@ 2023-08-01 16:50 ` Roger Quadros
0 siblings, 0 replies; 14+ messages in thread
From: Roger Quadros @ 2023-08-01 16:50 UTC (permalink / raw)
To: Jayesh Choudhary, nm, vigneshr
Cc: s-vadapalli, afd, kristo, robh+dt, krzysztof.kozlowski+dt,
conor+dt, a-bhatia1, r-ravikumar, sabiya.d, devicetree,
linux-kernel, linux-arm-kernel
On 01/08/2023 10:00, Jayesh Choudhary wrote:
> From: Rahul T R <r-ravikumar@ti.com>
>
> Add DSS and DP-bridge node for J784S4 SoC. DSS IP in J784S4 is
> same as DSS IP in J721E, so same compatible is being used.
> The DP is Cadence MHDP8546.
>
> Signed-off-by: Rahul T R <r-ravikumar@ti.com>
> [j-choudhary@ti.com: move dss & mhdp node together in main, fix dss node]
> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
> ---
> arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 73 ++++++++++++++++++++++
> 1 file changed, 73 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> index fbf5ab94d785..975661948755 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> @@ -1749,4 +1749,77 @@ c71_3: dsp@67800000 {
> resets = <&k3_reset 40 1>;
> firmware-name = "j784s4-c71_3-fw";
> };
> +
> + mhdp: dp-bridge@a000000 {
bridge@a000000
> + compatible = "ti,j721e-mhdp8546";
> +
why the new lines all over the place within nodes?
> + reg = <0x0 0xa000000 0x0 0x30a00>,
> + <0x0 0x4f40000 0x0 0x20>;
> + reg-names = "mhdptx", "j721e-intg";
> +
> + clocks = <&k3_clks 217 11>;
> +
> + interrupt-parent = <&gic500>;
> + interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
> +
> + power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
> +
> + status = "disabled";
> +
> + dp0_ports: ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + dss: dss@4a00000 {
> + compatible = "ti,j721e-dss";
> + reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */
> + <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
> + <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
> + <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
> + <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
> + <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
> + <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
> + <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
> + <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
> + <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
> + <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
> + <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
> + <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
> + <0x00 0x04aa0000 0x00 0x10000>, /* vp1 */
> + <0x00 0x04ac0000 0x00 0x10000>, /* vp1 */
> + <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
> + <0x00 0x04af0000 0x00 0x10000>; /* wb */
> +
> + reg-names = "common_m", "common_s0",
> + "common_s1", "common_s2",
> + "vidl1", "vidl2","vid1","vid2",
> + "ovr1", "ovr2", "ovr3", "ovr4",
> + "vp1", "vp2", "vp3", "vp4",
> + "wb";
> +
> + clocks = <&k3_clks 218 0>,
> + <&k3_clks 218 2>,
> + <&k3_clks 218 5>,
> + <&k3_clks 218 14>,
> + <&k3_clks 218 18>;
> + clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
> +
> + power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
> +
> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "common_m",
> + "common_s0",
> + "common_s1",
> + "common_s2";
> +
> + status = "disabled";
> +
> + dss_ports: ports {
> + };
> + };
> };
--
cheers,
-roger
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v8 2/5] arm64: dts: ti: k3-j784s4-main: Add WIZ and SERDES PHY nodes
2023-08-01 7:00 ` [PATCH v8 2/5] arm64: dts: ti: k3-j784s4-main: Add WIZ and SERDES PHY nodes Jayesh Choudhary
@ 2023-08-01 16:56 ` Roger Quadros
2023-08-03 5:37 ` Jayesh Choudhary
0 siblings, 1 reply; 14+ messages in thread
From: Roger Quadros @ 2023-08-01 16:56 UTC (permalink / raw)
To: Jayesh Choudhary, nm, vigneshr
Cc: s-vadapalli, afd, kristo, robh+dt, krzysztof.kozlowski+dt,
conor+dt, a-bhatia1, r-ravikumar, sabiya.d, devicetree,
linux-kernel, linux-arm-kernel
On 01/08/2023 10:00, Jayesh Choudhary wrote:
> From: Siddharth Vadapalli <s-vadapalli@ti.com>
>
> J784S4 SoC has 4 Serdes instances along with their respective WIZ
> instances. Add device-tree nodes for them and disable them by default.
>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> [j-choudhary@ti.com: fix serdes_wiz clock order & disable serdes refclk]
> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
> ---
> arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 172 +++++++++++++++++++++
> 1 file changed, 172 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> index 8a816563706b..fbf5ab94d785 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> @@ -6,9 +6,19 @@
> */
>
> #include <dt-bindings/mux/mux.h>
> +#include <dt-bindings/phy/phy.h>
> +#include <dt-bindings/phy/phy-ti.h>
>
> #include "k3-serdes.h"
>
> +/ {
> + serdes_refclk: serdes-refclk {
standard name should begin with clock
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + status = "disabled";
> + };
> +};
> +
> &cbass_main {
> msmc_ram: sram@70000000 {
> compatible = "mmio-sram";
> @@ -709,6 +719,168 @@ main_sdhci1: mmc@4fb0000 {
> status = "disabled";
> };
>
> + serdes_wiz0: wiz@5060000 {
> + compatible = "ti,j784s4-wiz-10g";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + power-domains = <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 404 2>, <&k3_clks 404 6>, <&serdes_refclk>, <&k3_clks 404 5>;
> + clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
> + assigned-clocks = <&k3_clks 404 6>;
> + assigned-clock-parents = <&k3_clks 404 10>;
> + num-lanes = <4>;
> + #reset-cells = <1>;
> + #clock-cells = <1>;
> + ranges = <0x5060000 0x00 0x5060000 0x10000>;
> +> + status = "disabled";
> +
drop blank lines here and rest of this file where you set status to "disabled".
> + serdes0: serdes@5060000 {
phy@5060000
> + compatible = "ti,j721e-serdes-10g";
> + reg = <0x05060000 0x010000>;
> + reg-names = "torrent_phy";
> + resets = <&serdes_wiz0 0>;
> + reset-names = "torrent_reset";
> + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
> + clock-names = "refclk", "phy_en_refclk";
> + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
> + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
> + assigned-clock-parents = <&k3_clks 404 6>,
> + <&k3_clks 404 6>,
> + <&k3_clks 404 6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #clock-cells = <1>;
> +
> + status = "disabled";
> + };
> + };
> +
> + serdes_wiz1: wiz@5070000 {
> + compatible = "ti,j784s4-wiz-10g";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + power-domains = <&k3_pds 405 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 405 2>, <&k3_clks 405 6>, <&serdes_refclk>, <&k3_clks 405 5>;
> + clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
> + assigned-clocks = <&k3_clks 405 6>;
> + assigned-clock-parents = <&k3_clks 405 10>;
> + num-lanes = <4>;
> + #reset-cells = <1>;
> + #clock-cells = <1>;
> + ranges = <0x05070000 0x00 0x05070000 0x10000>;
> +
> + status = "disabled";
> +
> + serdes1: serdes@5070000 {
phy@5070000
> + compatible = "ti,j721e-serdes-10g";
> + reg = <0x05070000 0x010000>;
> + reg-names = "torrent_phy";
> + resets = <&serdes_wiz1 0>;
> + reset-names = "torrent_reset";
> + clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
> + clock-names = "refclk", "phy_en_refclk";
> + assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
> + <&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
> + assigned-clock-parents = <&k3_clks 405 6>,
> + <&k3_clks 405 6>,
> + <&k3_clks 405 6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #clock-cells = <1>;
> +
> + status = "disabled";
> + };
> + };
> +
> + serdes_wiz2: wiz@5020000 {
> + compatible = "ti,j784s4-wiz-10g";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + power-domains = <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 406 2>, <&k3_clks 406 6>, <&serdes_refclk>, <&k3_clks 406 5>;
> + clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
> + assigned-clocks = <&k3_clks 406 6>;
> + assigned-clock-parents = <&k3_clks 406 10>;
> + num-lanes = <4>;
> + #reset-cells = <1>;
> + #clock-cells = <1>;
> + ranges = <0x05020000 0x00 0x05020000 0x10000>;
> +
> + status = "disabled";
> +
> + serdes2: serdes@5020000 {
phy@5020000
> + compatible = "ti,j721e-serdes-10g";
> + reg = <0x05020000 0x010000>;
> + reg-names = "torrent_phy";
> + resets = <&serdes_wiz2 0>;
> + reset-names = "torrent_reset";
> + clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>;
> + clock-names = "refclk", "phy_en_refclk";
> + assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>,
> + <&serdes_wiz2 TI_WIZ_REFCLK_DIG>;
> + assigned-clock-parents = <&k3_clks 406 6>,
> + <&k3_clks 406 6>,
> + <&k3_clks 406 6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #clock-cells = <1>;
> +
> + status = "disabled";
> + };
> + };
> +
> + serdes_wiz4: wiz@5050000 {
> + compatible = "ti,j784s4-wiz-10g";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + power-domains = <&k3_pds 407 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 407 2>, <&k3_clks 407 6>, <&serdes_refclk>, <&k3_clks 407 5>;
> + clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
> + assigned-clocks = <&k3_clks 407 6>;
> + assigned-clock-parents = <&k3_clks 407 10>;
> + num-lanes = <4>;
> + #reset-cells = <1>;
> + #clock-cells = <1>;
> + ranges = <0x05050000 0x00 0x05050000 0x10000>,
> + <0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */
> +
> + status = "disabled";
> +
> + serdes4: serdes@5050000 {
phy@5050000
> + /*
> + * Note: we also map DPTX PHY registers as the Torrent
> + * needs to manage those.
> + */
> + compatible = "ti,j721e-serdes-10g";
> + reg = <0x05050000 0x010000>,
> + <0x0a030a00 0x40>; /* DPTX PHY */
> + reg-names = "torrent_phy";
> + resets = <&serdes_wiz4 0>;
> + reset-names = "torrent_reset";
> + clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>;
> + clock-names = "refclk", "phy_en_refclk";
> + assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
> + <&serdes_wiz4 TI_WIZ_REFCLK_DIG>;
> + assigned-clock-parents = <&k3_clks 407 6>,
> + <&k3_clks 407 6>,
> + <&k3_clks 407 6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #clock-cells = <1>;
> +
> + status = "disabled";
> + };
> + };
> +
> main_navss: bus@30000000 {
> compatible = "simple-bus";
> #address-cells = <2>;
--
cheers,
-roger
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v8 5/5] arm64: dts: ti: k3-am69-sk: Add DP and HDMI support
2023-08-01 16:48 ` Roger Quadros
@ 2023-08-01 16:58 ` Roger Quadros
2023-08-03 5:26 ` Jayesh Choudhary
0 siblings, 1 reply; 14+ messages in thread
From: Roger Quadros @ 2023-08-01 16:58 UTC (permalink / raw)
To: Jayesh Choudhary, nm, vigneshr, tomba
Cc: s-vadapalli, afd, kristo, robh+dt, krzysztof.kozlowski+dt,
conor+dt, a-bhatia1, r-ravikumar, sabiya.d, devicetree,
linux-kernel, linux-arm-kernel
+Tomi (fixed email)
Need to fix this in
Documentation/devicetree/bindings/display/bridge/ti,tfp410.yaml
On 01/08/2023 19:48, Roger Quadros wrote:
>
>
> On 01/08/2023 10:00, Jayesh Choudhary wrote:
>> From: Dasnavis Sabiya <sabiya.d@ti.com>
>>
>> AM69 starter kit features an HDMI port and an eDP port.
>>
>> Add assigned clocks for DSS, DT node for DisplayPort PHY,
>> pinmux for HDMI hotplug and power down, mcu_i2c1 and dss_vout
>> for HDMI.
>> Also enable Serdes4 settings for DP display.
>>
>> Add the endpoint nodes to describe connection from:
>> DSS => MHDP => DisplayPort connector
>> DSS => TI TFP410 DPI-to-DVI Bridge => HDMI connector
>>
>> Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com>
>> [j-choudhary@ti.com: Fix dvi-bridge, dss, mhdp and serdes-refclk]
>> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
>> ---
>> arch/arm64/boot/dts/ti/k3-am69-sk.dts | 237 ++++++++++++++++++++++++++
>> 1 file changed, 237 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts
>> index d282c2c633c1..d9a0794bcf6e 100644
>> --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts
>> +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts
>> @@ -107,6 +107,83 @@ vdd_sd_dv: regulator-tlv71033 {
>> states = <1800000 0x0>,
>> <3300000 0x1>;
>> };
>> +
>> + dp0_pwr_3v3: regulator {
>
> To be consistent with the rest of the file please
> use regulator-dp0-pwr
>
>> + compatible = "regulator-fixed";
>> + regulator-name = "dp0-pwr";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&dp_pwr_en_pins_default>;
>> + gpio = <&main_gpio0 4 0>; /* DP0_3V3 _EN */
>> + enable-active-high;
>> + };
>> +
>> + dp0: connector {
>
> connector-dp0
>
>> + compatible = "dp-connector";
>> + label = "DP0";
>> + type = "full-size";
>> + dp-pwr-supply = <&dp0_pwr_3v3>;
>> +
>> + port {
>> + dp0_connector_in: endpoint {
>> + remote-endpoint = <&dp0_out>;
>> + };
>> + };
>> + };
>> +
>> + hdmi-connector {
>
> connector-hdmi
>
>> + compatible = "hdmi-connector";
>> + label = "hdmi";
>> + type = "a";
>> +
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&hdmi_hpd_pins_default>;
>> +
>> + ddc-i2c-bus = <&mcu_i2c1>;
>> +
>> + /* HDMI_HPD */
>> + hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>;
>> +
>> + port {
>> + hdmi_connector_in: endpoint {
>> + remote-endpoint = <&tfp410_out>;
>> + };
>> + };
>> + };
>> +
>> + dvi-bridge {
>
> Although DT binding doc for ti,tfp410 says encoder
> a name starting with bridge maybe more appropriate.
>
>> + compatible = "ti,tfp410";
>> +
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&hdmi_pdn_pins_default>;
>> +
>> + /* HDMI_PDn */
>> + powerdown-gpios = <&wkup_gpio0 14 GPIO_ACTIVE_LOW>;
>> + ti,deskew = <0>;
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> +
>> + tfp410_in: endpoint {
>> + remote-endpoint = <&dpi1_out0>;
>> + pclk-sample = <1>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> +
>> + tfp410_out: endpoint {
>> + remote-endpoint = <&hdmi_connector_in>;
>> + };
>> + };
>> + };
>> + };
>> };
>>
>> &main_pmx0 {
>> @@ -161,6 +238,57 @@ J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.GPIO0_2 */
>> J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */
>> >;
>> };
>> +
>> + dp0_pins_default: dp0-pins-default {
>> + pinctrl-single,pins = <
>> + J784S4_IOPAD(0x014, PIN_INPUT, 13) /* (AG33) MCAN14_TX.DP0_HPD */
>> + >;
>> + };
>> +
>> + dp_pwr_en_pins_default: dp-pwr-en-pins-default {
>> + pinctrl-single,pins = <
>> + J784S4_IOPAD(0x010, PIN_INPUT, 7) /* (AH33) MCAN13_RX.GPIO0_4 */
>> + >;
>> + };
>> +
>> + dss_vout0_pins_default: dss-vout0-pins-default {
>> + pinctrl-single,pins = <
>> + J784S4_IOPAD(0x074, PIN_OUTPUT, 2) /* (AC33) MCAN2_TX.VOUT0_DATA0 */
>> + J784S4_IOPAD(0x070, PIN_OUTPUT, 2) /* (AH38) MCAN1_RX.VOUT0_DATA1 */
>> + J784S4_IOPAD(0x07c, PIN_OUTPUT, 2) /* (AJ38) MCASP0_AXR3.VOUT0_DATA2 */
>> + J784S4_IOPAD(0x068, PIN_OUTPUT, 2) /* (AE38) MCAN0_RX.VOUT0_DATA3 */
>> + J784S4_IOPAD(0x064, PIN_OUTPUT, 2) /* (AF38) MCAN0_TX.VOUT0_DATA4 */
>> + J784S4_IOPAD(0x060, PIN_OUTPUT, 2) /* (AE36) MCASP2_AXR1.VOUT0_DATA5 */
>> + J784S4_IOPAD(0x05c, PIN_OUTPUT, 2) /* (AC36) MCASP2_AXR0.VOUT0_DATA6 */
>> + J784S4_IOPAD(0x058, PIN_OUTPUT, 2) /* (AE37) MCASP2_AFSX.VOUT0_DATA7 */
>> + J784S4_IOPAD(0x054, PIN_OUTPUT, 2) /* (AD37) MCASP2_ACLKX.VOUT0_DATA8 */
>> + J784S4_IOPAD(0x050, PIN_OUTPUT, 2) /* (AC37) MCASP1_AXR2.VOUT0_DATA9 */
>> + J784S4_IOPAD(0x04c, PIN_OUTPUT, 2) /* (AC32) MCASP1_AXR1.VOUT0_DATA10 */
>> + J784S4_IOPAD(0x048, PIN_OUTPUT, 2) /* (AK33) MCASP0_AXR2.VOUT0_DATA11 */
>> + J784S4_IOPAD(0x044, PIN_OUTPUT, 2) /* (AG37) MCASP0_AXR1.VOUT0_DATA12 */
>> + J784S4_IOPAD(0x040, PIN_OUTPUT, 2) /* (AF37) MCASP0_AXR0.VOUT0_DATA13 */
>> + J784S4_IOPAD(0x03c, PIN_OUTPUT, 2) /* (AK38) MCASP0_AFSX.VOUT0_DATA14 */
>> + J784S4_IOPAD(0x038, PIN_OUTPUT, 2) /* (AK35) MCASP0_ACLKX.VOUT0_DATA15 */
>> + J784S4_IOPAD(0x0c8, PIN_OUTPUT, 2) /* (AJ32) EXT_REFCLK1.VOUT0_DATA16 */
>> + J784S4_IOPAD(0x030, PIN_OUTPUT, 2) /* (AK37) GPIO0_12.VOUT0_DATA17 */
>> + J784S4_IOPAD(0x02c, PIN_OUTPUT, 2) /* (AL32) GPIO0_11.VOUT0_DATA18 */
>> + J784S4_IOPAD(0x028, PIN_OUTPUT, 2) /* (AE33) MCAN16_RX.VOUT0_DATA19 */
>> + J784S4_IOPAD(0x024, PIN_OUTPUT, 2) /* (AH34) MCAN16_TX.VOUT0_DATA20 */
>> + J784S4_IOPAD(0x020, PIN_OUTPUT, 2) /* (AJ35) MCAN15_RX.VOUT0_DATA21 */
>> + J784S4_IOPAD(0x01c, PIN_OUTPUT, 2) /* (AG34) MCAN15_TX.VOUT0_DATA22 */
>> + J784S4_IOPAD(0x018, PIN_OUTPUT, 2) /* (AK36) MCAN14_RX.VOUT0_DATA23 */
>> + J784S4_IOPAD(0x084, PIN_OUTPUT, 2) /* (AG38) MCASP0_AXR5.VOUT0_DE */
>> + J784S4_IOPAD(0x080, PIN_OUTPUT, 2) /* (AK34) MCASP0_AXR4.VOUT0_HSYNC */
>> + J784S4_IOPAD(0x078, PIN_OUTPUT, 2) /* (AH37) MCAN2_RX.VOUT0_PCLK */
>> + J784S4_IOPAD(0x088, PIN_OUTPUT, 2) /* (AF36) MCASP0_AXR6.VOUT0_VSYNC */
>> + >;
>> + };
>> +
>> + hdmi_hpd_pins_default: hdmi-hpd-pins-default {
>> + pinctrl-single,pins = <
>> + J784S4_IOPAD(0x000, PIN_INPUT, 7) /* (AN35) EXTINTN.GPIO0_0 */
>> + >;
>> + };
>> };
>>
>> &wkup_pmx2 {
>> @@ -231,6 +359,21 @@ J784S4_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (J36) WKUP_GPIO0_3 */
>> J784S4_WKUP_IOPAD(0x11c, PIN_INPUT, 7) /* (M34) WKUP_GPIO0_67 */
>> >;
>> };
>> +
>> + mcu_i2c1_pins_default: mcu-i2c1-pins-default {
>> + pinctrl-single,pins = <
>> + /* (L35) WKUP_GPIO0_8.MCU_I2C1_SCL */
>> + J784S4_WKUP_IOPAD(0x078, PIN_INPUT_PULLUP, 0)
>> + /* (L34) WKUP_GPIO0_9.MCU_I2C1_SDA */
>> + J784S4_WKUP_IOPAD(0x07c, PIN_INPUT_PULLUP, 0)
>> + >;
>> + };
>> +
>> + hdmi_pdn_pins_default: hdmi-pdn-pins-default {
>> + pinctrl-single,pins = <
>> + J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 7) /* (H37) WKUP_GPIO0_14 */
>> + >;
>> + };
>> };
>>
>> &wkup_pmx3 {
>> @@ -350,3 +493,97 @@ &mcu_cpsw_port1 {
>> phy-mode = "rgmii-rxid";
>> phy-handle = <&mcu_phy0>;
>> };
>> +
>> +&wkup_gpio_intr {
>> + status = "okay";
>> +};
>> +
>> +&mcu_i2c1 {
>> + status = "okay";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&mcu_i2c1_pins_default>;
>> + clock-frequency = <100000>;
>> +};
>> +
>> +&serdes_refclk {
>> + status = "okay";
>> + clock-frequency = <100000000>;
>> +};
>> +
>> +&dss {
>> + status = "okay";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&dss_vout0_pins_default>;
>> + assigned-clocks = <&k3_clks 218 2>,
>> + <&k3_clks 218 5>,
>> + <&k3_clks 218 14>,
>> + <&k3_clks 218 18>;
>> + assigned-clock-parents = <&k3_clks 218 3>,
>> + <&k3_clks 218 7>,
>> + <&k3_clks 218 16>,
>> + <&k3_clks 218 22>;
>> +};
>> +
>> +&serdes_wiz4 {
>> + status = "okay";
>> +};
>> +
>> +&serdes4 {
>> + status = "okay";
>> + serdes4_dp_link: phy@0 {
>> + reg = <0>;
>> + cdns,num-lanes = <4>;
>> + #phy-cells = <0>;
>> + cdns,phy-type = <PHY_TYPE_DP>;
>> + resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>,
>> + <&serdes_wiz4 3>, <&serdes_wiz4 4>;
>> + };
>> +};
>> +
>> +&mhdp {
>> + status = "okay";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&dp0_pins_default>;
>> + phys = <&serdes4_dp_link>;
>> + phy-names = "dpphy";
>> +};
>> +
>> +&dss_ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + /* DP */
>> + port@0 {
>> + reg = <0>;
>> + dpi0_out: endpoint {
>> + remote-endpoint = <&dp0_in>;
>> + };
>> + };
>> +
>> + /* HDMI */
>> + port@1 {
>> + reg = <1>;
>> + dpi1_out0: endpoint {
>> + remote-endpoint = <&tfp410_in>;
>> + };
>> + };
>> +};
>> +
>> +&dp0_ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + dp0_in: endpoint {
>> + remote-endpoint = <&dpi0_out>;
>> + };
>> + };
>> +
>> + port@4 {
>> + reg = <4>;
>> + dp0_out: endpoint {
>> + remote-endpoint = <&dp0_connector_in>;
>> + };
>> + };
>> +};
>
--
cheers,
-roger
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v8 5/5] arm64: dts: ti: k3-am69-sk: Add DP and HDMI support
2023-08-01 16:58 ` Roger Quadros
@ 2023-08-03 5:26 ` Jayesh Choudhary
0 siblings, 0 replies; 14+ messages in thread
From: Jayesh Choudhary @ 2023-08-03 5:26 UTC (permalink / raw)
To: Roger Quadros, nm, vigneshr, tomba
Cc: s-vadapalli, afd, kristo, robh+dt, krzysztof.kozlowski+dt,
conor+dt, a-bhatia1, r-ravikumar, sabiya.d, devicetree,
linux-kernel, linux-arm-kernel
Hello Roger,
On 01/08/23 22:28, Roger Quadros wrote:
> +Tomi (fixed email)
>
> Need to fix this in
> Documentation/devicetree/bindings/display/bridge/ti,tfp410.yaml
>
> On 01/08/2023 19:48, Roger Quadros wrote:
>>
>>
>> On 01/08/2023 10:00, Jayesh Choudhary wrote:
>>> From: Dasnavis Sabiya <sabiya.d@ti.com>
>>>
>>> AM69 starter kit features an HDMI port and an eDP port.
>>>
>>> Add assigned clocks for DSS, DT node for DisplayPort PHY,
>>> pinmux for HDMI hotplug and power down, mcu_i2c1 and dss_vout
>>> for HDMI.
>>> Also enable Serdes4 settings for DP display.
>>>
>>> Add the endpoint nodes to describe connection from:
>>> DSS => MHDP => DisplayPort connector
>>> DSS => TI TFP410 DPI-to-DVI Bridge => HDMI connector
>>>
>>> Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com>
>>> [j-choudhary@ti.com: Fix dvi-bridge, dss, mhdp and serdes-refclk]
>>> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
>>> ---
>>> arch/arm64/boot/dts/ti/k3-am69-sk.dts | 237 ++++++++++++++++++++++++++
>>> 1 file changed, 237 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts
>>> index d282c2c633c1..d9a0794bcf6e 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts
>>> +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts
>>> @@ -107,6 +107,83 @@ vdd_sd_dv: regulator-tlv71033 {
>>> states = <1800000 0x0>,
>>> <3300000 0x1>;
>>> };
>>> +
>>> + dp0_pwr_3v3: regulator {
>>
>> To be consistent with the rest of the file please
>> use regulator-dp0-pwr
Sure.
>>
>>> + compatible = "regulator-fixed";
>>> + regulator-name = "dp0-pwr";
>>> + regulator-min-microvolt = <3300000>;
>>> + regulator-max-microvolt = <3300000>;
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&dp_pwr_en_pins_default>;
>>> + gpio = <&main_gpio0 4 0>; /* DP0_3V3 _EN */
>>> + enable-active-high;
>>> + };
>>> +
>>> + dp0: connector {
>>
>> connector-dp0
Ok
>>
>>> + compatible = "dp-connector";
>>> + label = "DP0";
>>> + type = "full-size";
>>> + dp-pwr-supply = <&dp0_pwr_3v3>;
>>> +
>>> + port {
>>> + dp0_connector_in: endpoint {
>>> + remote-endpoint = <&dp0_out>;
>>> + };
>>> + };
>>> + };
>>> +
>>> + hdmi-connector {
>>
>> connector-hdmi
Ok.
>>
>>> + compatible = "hdmi-connector";
>>> + label = "hdmi";
>>> + type = "a";
>>> +
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&hdmi_hpd_pins_default>;
>>> +
>>> + ddc-i2c-bus = <&mcu_i2c1>;
>>> +
>>> + /* HDMI_HPD */
>>> + hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>;
>>> +
>>> + port {
>>> + hdmi_connector_in: endpoint {
>>> + remote-endpoint = <&tfp410_out>;
>>> + };
>>> + };
>>> + };
>>> +
>>> + dvi-bridge {
>>
>> Although DT binding doc for ti,tfp410 says encoder
>> a name starting with bridge maybe more appropriate.
Will keep it as bridge-dvi.
Will edit the node names in suggested in 3/5 and 4/5 as well.
I will address the new-line comments too.
Thanks
-Jayesh
>>
[...]
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v8 2/5] arm64: dts: ti: k3-j784s4-main: Add WIZ and SERDES PHY nodes
2023-08-01 16:56 ` Roger Quadros
@ 2023-08-03 5:37 ` Jayesh Choudhary
0 siblings, 0 replies; 14+ messages in thread
From: Jayesh Choudhary @ 2023-08-03 5:37 UTC (permalink / raw)
To: Roger Quadros, nm, vigneshr
Cc: s-vadapalli, afd, kristo, robh+dt, krzysztof.kozlowski+dt,
conor+dt, a-bhatia1, r-ravikumar, sabiya.d, devicetree,
linux-kernel, linux-arm-kernel
Hello Roger,
On 01/08/23 22:26, Roger Quadros wrote:
>
>
> On 01/08/2023 10:00, Jayesh Choudhary wrote:
>> From: Siddharth Vadapalli <s-vadapalli@ti.com>
>>
>> J784S4 SoC has 4 Serdes instances along with their respective WIZ
>> instances. Add device-tree nodes for them and disable them by default.
>>
>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
>> [j-choudhary@ti.com: fix serdes_wiz clock order & disable serdes refclk]
>> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
>> ---
>> arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 172 +++++++++++++++++++++
>> 1 file changed, 172 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>> index 8a816563706b..fbf5ab94d785 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>> @@ -6,9 +6,19 @@
>> */
>>
>> #include <dt-bindings/mux/mux.h>
>> +#include <dt-bindings/phy/phy.h>
>> +#include <dt-bindings/phy/phy-ti.h>
>>
>> #include "k3-serdes.h"
>>
>> +/ {
>> + serdes_refclk: serdes-refclk {
>
> standard name should begin with clock
>
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + status = "disabled";
>> + };
>> +};
>> +
>> &cbass_main {
>> msmc_ram: sram@70000000 {
>> compatible = "mmio-sram";
>> @@ -709,6 +719,168 @@ main_sdhci1: mmc@4fb0000 {
>> status = "disabled";
>> };
>>
>> + serdes_wiz0: wiz@5060000 {
>> + compatible = "ti,j784s4-wiz-10g";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + power-domains = <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>;
>> + clocks = <&k3_clks 404 2>, <&k3_clks 404 6>, <&serdes_refclk>, <&k3_clks 404 5>;
>> + clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
>> + assigned-clocks = <&k3_clks 404 6>;
>> + assigned-clock-parents = <&k3_clks 404 10>;
>> + num-lanes = <4>;
>> + #reset-cells = <1>;
>> + #clock-cells = <1>;
>> + ranges = <0x5060000 0x00 0x5060000 0x10000>;
>> +> + status = "disabled";
>> +
> drop blank lines here and rest of this file where you set status to "disabled".
>
>> + serdes0: serdes@5060000 {
>
> phy@5060000
According to the bindings, serdes is valid.
(./Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml)
It would throw dtbs_check errors with phy@.
If its a binding change that you are suggesting, then it can be picked
up later on for all platform at once.
So keeping it as serdes@50*0000 on all the suggested places.
>
>> + compatible = "ti,j721e-serdes-10g";
>> + reg = <0x05060000 0x010000>;
[...]
>> +
>> + serdes1: serdes@5070000 {
>
> phy@5070000
>> + compatible = "ti,j721e-serdes-10g";
>> + reg = <0x05070000 0x010000>;
>> + reg-names = "torrent_phy";
[...]
>> +
>> + status = "disabled";
>> +
>> + serdes2: serdes@5020000 {
>
> phy@5020000
>
>> + compatible = "ti,j721e-serdes-10g";
>> + reg = <0x05020000 0x010000>;
[...]
>> + status = "disabled";
>> +
>> + serdes4: serdes@5050000 {
>
> phy@5050000
>
>> + /*
[...]
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^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2023-08-03 5:38 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-08-01 7:00 [PATCH v8 0/5] Enable Display for J784S4 and AM69-SK platform Jayesh Choudhary
2023-08-01 7:00 ` [PATCH v8 1/5] arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux Jayesh Choudhary
2023-08-01 14:19 ` Andrew Davis
2023-08-01 7:00 ` [PATCH v8 2/5] arm64: dts: ti: k3-j784s4-main: Add WIZ and SERDES PHY nodes Jayesh Choudhary
2023-08-01 16:56 ` Roger Quadros
2023-08-03 5:37 ` Jayesh Choudhary
2023-08-01 7:00 ` [PATCH v8 3/5] arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node Jayesh Choudhary
2023-08-01 16:50 ` Roger Quadros
2023-08-01 7:00 ` [PATCH v8 4/5] arm64: dts: ti: k3-j784s4-evm: Enable DisplayPort-0 Jayesh Choudhary
2023-08-01 16:40 ` Roger Quadros
2023-08-01 7:00 ` [PATCH v8 5/5] arm64: dts: ti: k3-am69-sk: Add DP and HDMI support Jayesh Choudhary
2023-08-01 16:48 ` Roger Quadros
2023-08-01 16:58 ` Roger Quadros
2023-08-03 5:26 ` Jayesh Choudhary
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