From: "SkyLake Huang (黃啟澤)" <SkyLake.Huang@mediatek.com>
To: "daniel@makrotopia.org" <daniel@makrotopia.org>
Cc: "andrew@lunn.ch" <andrew@lunn.ch>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-mediatek@lists.infradead.org"
<linux-mediatek@lists.infradead.org>,
"linux@armlinux.org.uk" <linux@armlinux.org.uk>,
"kuba@kernel.org" <kuba@kernel.org>,
"pabeni@redhat.com" <pabeni@redhat.com>,
"edumazet@google.com" <edumazet@google.com>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"dqfext@gmail.com" <dqfext@gmail.com>,
"Steven Liu (劉人豪)" <steven.liu@mediatek.com>,
"matthias.bgg@gmail.com" <matthias.bgg@gmail.com>,
"davem@davemloft.net" <davem@davemloft.net>,
"hkallweit1@gmail.com" <hkallweit1@gmail.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"angelogioacchino.delregno@collabora.com"
<angelogioacchino.delregno@collabora.com>
Subject: Re: [PATCH net-next v6 5/5] net: phy: add driver for built-in 2.5G ethernet PHY on MT7988
Date: Tue, 4 Jun 2024 08:57:55 +0000 [thread overview]
Message-ID: <b7ee870be0ecee7eacfbd1424356d2e8fe369cec.camel@mediatek.com> (raw)
In-Reply-To: <Zl4cE2yc5MuJSZJ6@makrotopia.org>
On Mon, 2024-06-03 at 20:40 +0100, Daniel Golle wrote:
>
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> On Mon, Jun 03, 2024 at 08:18:34PM +0800, Sky Huang wrote:
> > From: "SkyLake.Huang" <skylake.huang@mediatek.com>
> > +
> > +static int mt798x_2p5ge_phy_get_rate_matching(struct phy_device
> *phydev,
> > + phy_interface_t iface)
> > +{
> > +if (iface == PHY_INTERFACE_MODE_XGMII ||
> > + iface == PHY_INTERFACE_MODE_INTERNAL)
> > +return RATE_MATCH_PAUSE;
> > +return RATE_MATCH_NONE;
>
> As the phy is always connected in the same way internally inside the
> MT7988
> this check and destinction doesn't make sense to me.
>
> Imho you should always return RATE_MATCH_PAUSE, unless the same PHY
> also
> exists in other SoCs and/or is connected in different interface
> modes.
>
> In any way, please explain this part to us, especially in which
> situation
> exactly you want to return RATE_MATCH_NONE and for which reason.
>
Actually internal 2.5Gphy is planned to be conntected to both XFI-MAC
and GMAC at very first: (2.5G speed relies on XGMII path and
1G/100M/10M rely on GMII/MII path)
+---------+ +--------+
| | | |
| XFI-MAC | | GMAC |
| | | |
+---------+ +--------+
| |
| |
(FCM) |
+-------+----------+
| XGMII | GMII/MII |
+------------------+
| |
| built-in |
| 2.5Gphy |
| |
+------------------+
This phy's rate adaptation is implemented in FCM (flow control
module) on the XGMII path. So mt798x_2p5ge_phy_get_rate_matching() will
only return RATE_MATCH_PAUSE for this path.(for developing purpose)
However, GMII/MII is deprecated later in our built-in 2.5Gphy
hardware design. So yes, you're right.
mt798x_2p5ge_phy_get_rate_matching() should always return
RATE_MATCH_PAUSE now. I'll change this in next version.
Sky
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prev parent reply other threads:[~2024-06-04 8:58 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-03 12:18 [PATCH net-next v6 0/5] net: phy: mediatek: Introduce mtk-phy-lib and add 2.5Gphy support Sky Huang
2024-06-03 12:18 ` [PATCH net-next v6 1/5] net: phy: mediatek: Re-organize MediaTek ethernet phy drivers Sky Huang
2024-06-03 12:18 ` [PATCH net-next v6 2/5] net: phy: mediatek: Move LED and read/write page helper functions into mtk phy lib Sky Huang
2024-06-03 12:18 ` [PATCH net-next v6 3/5] net: phy: mediatek: Add token ring access helper functions in mtk-phy-lib Sky Huang
2024-06-03 12:18 ` [PATCH net-next v6 4/5] net: phy: mediatek: Extend 1G TX/RX link pulse time Sky Huang
2024-06-03 12:18 ` [PATCH net-next v6 5/5] net: phy: add driver for built-in 2.5G ethernet PHY on MT7988 Sky Huang
2024-06-03 13:25 ` Russell King (Oracle)
2024-06-03 13:31 ` Daniel Golle
2024-06-03 13:41 ` Russell King (Oracle)
2024-06-03 14:52 ` Daniel Golle
2024-06-03 15:47 ` Russell King (Oracle)
2024-06-03 17:00 ` Daniel Golle
2024-06-03 18:30 ` Russell King (Oracle)
2024-06-04 8:42 ` SkyLake Huang (黃啟澤)
2024-06-04 13:50 ` Daniel Golle
2024-06-13 10:28 ` SkyLake Huang (黃啟澤)
2024-06-13 13:33 ` Andrew Lunn
2024-06-03 19:40 ` Daniel Golle
2024-06-04 8:57 ` SkyLake Huang (黃啟澤) [this message]
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