From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 40401C76195 for ; Mon, 27 Mar 2023 14:24:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:Cc:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9AVSvpEDZEFJ8S59ZC+OyspO8h0LwIBpIOVV5N5G8Ng=; b=nsh6trgsiKFvaD 1Vjrxkj1LepcbYPycoeAPIRfpfwtwL6/I8sq9jMlNIIm4chVrExixdCL3izvpCPYz1tsDaPCeI/gM 5YbfCl9TK1qxYZGTQanfWB6jZ3Uji2YdwxbCVFTyOGQYvlYdziv1pS6RbxIM3xmitzrDRQH6WOfPl 7lTTCHZeeG3b3pyGXwRkxf/kRHSCwbm78kXHFwkH+gduMWUKCLbk1fZE4pqWea6qzg8nchzKoJigF p3Rf0+iB83g+8fOmO12C9kIf/0FmwrUzfApiQBGxtohcVNH5RDjfKOiprTabHC6jhY8mv+xDreiRt 1RbD0j62+usJ0uj1OfQA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pgnkr-00BJHb-0i; Mon, 27 Mar 2023 14:23:25 +0000 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pgnko-00BJG9-2X for linux-arm-kernel@lists.infradead.org; Mon, 27 Mar 2023 14:23:24 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1679927000; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=eX1ybBpnNpLzda+u/YuamQ+WYiivy4DRAIsglCG/Ipk=; b=azSBnaV94B5JYbtrRewEGWZEyXv0yEEjySNr/jlIT3VI0KCF4XaopbDGRVBr0sAlwh95Ld rtA9IZiUfIzHdEnwa52wMCOeYjePeRw2VPNlHyDSYwXzkQqCXM1auhH60qlOEQ/E+15dav Fz/B5pLU2743IOBgvYEfhvwCQWGvvwQ= Received: from mail-qk1-f197.google.com (mail-qk1-f197.google.com [209.85.222.197]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-295-TBXAEZRCMx-0CmuZTbZ_oA-1; Mon, 27 Mar 2023 10:23:18 -0400 X-MC-Unique: TBXAEZRCMx-0CmuZTbZ_oA-1 Received: by mail-qk1-f197.google.com with SMTP id s12-20020a37a90c000000b007468eaf866aso4066135qke.17 for ; Mon, 27 Mar 2023 07:23:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679926998; h=mime-version:user-agent:content-transfer-encoding:references :in-reply-to:date:cc:to:from:subject:message-id:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=eX1ybBpnNpLzda+u/YuamQ+WYiivy4DRAIsglCG/Ipk=; b=ACKkj8gqo2g051lEYjm4+ouZevVzaIkGpR+OjstPBy25VImjuw11O5BJzff7mvv2u0 ylOuDIZY7iAEVDBJk6sbwlkHRQfKEQn/1/O/cDGfKBRDIExisgaGBaJd6vJbaH1IST+m XoDvY7CbvSSqQFiFsePp1nkOGcDkRGBWikEGrFT6mtQTJkDQZD51KCvydjDTVjJixKTN m/KExmVp9J5PK7a4K+nmXH/TvJ/gsW8ygL0WXhSD4DzdGpQonORIbo3Ut85Au5B4ZSSH QqBclHda+9Nj3IwqwY+SDIaJLHA8BKNYN4xoIy/LnIqZqdJdbLn1RYvAQBP+MU97ub8m p/cQ== X-Gm-Message-State: AO0yUKXYbnNNLd4/WNoywoTvNmJh0TbDy9+hcM36ab7UI2Q7kkt2wpoX HuufFUp5Y2rYPYtSM/FIKUrg1LPptEZREQNJxqKS6qyNjDNB0OMUtTehz+Y1fFFX6yS6b8AKJGG o4mb70ausv1SqmMbQgbItYW4p7HoGKBDE9ro= X-Received: by 2002:ac8:5c16:0:b0:3df:50ef:fafa with SMTP id i22-20020ac85c16000000b003df50effafamr20500511qti.4.1679926998297; Mon, 27 Mar 2023 07:23:18 -0700 (PDT) X-Google-Smtp-Source: AK7set+Nuxr8wSNCpreLPGhvpyil9O3Bmh9ynJWjufbDNZ0aHwhKdNqGczpZrAodW48oTNwp5H8pxA== X-Received: by 2002:ac8:5c16:0:b0:3df:50ef:fafa with SMTP id i22-20020ac85c16000000b003df50effafamr20500466qti.4.1679926997833; Mon, 27 Mar 2023 07:23:17 -0700 (PDT) Received: from thinkpad-p1.localdomain (cpe00fc8d79db03-cm00fc8d79db00.cpe.net.fido.ca. [72.137.118.218]) by smtp.gmail.com with ESMTPSA id l6-20020ac848c6000000b003bfb0ea8094sm8299495qtr.83.2023.03.27.07.23.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 07:23:17 -0700 (PDT) Message-ID: Subject: Re: [RFC PATCH] arch_topology: Pre-allocate cacheinfo from primary CPU From: Radu Rendec To: Pierre Gondois , linux-arm-kernel@lists.infradead.org Cc: Sudeep Holla , Adrien Thierry , Eric Chanudet Date: Mon, 27 Mar 2023 10:23:16 -0400 In-Reply-To: References: <20230323224242.31142-1-rrendec@redhat.com> User-Agent: Evolution 3.46.4 (3.46.4-1.fc37) MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230327_072322_919359_36A5D1C2 X-CRM114-Status: GOOD ( 25.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 2023-03-27 at 14:02 +0200, Pierre Gondois wrote: > About populating the cache info from the CLIDR_EL1 register, it seems > the information might be incorrect for DT based system, and the mask > of L1 data/instruction caches could be advertised as private for > ACPI/DT based systems when no cache information is available. > There is a patch-set that should fix this at: > https://lore.kernel.org/all/20230327115953.788244-1-pierre.gondois@arm.com/ Hello Pierre, Thanks for pointing out this issue and creating a patch-set to fix it. I will keep an eye on it. This is definitely important, since we are planing to rely on the CLIDR_EL1 based detection. > On 3/23/23 23:42, Radu Rendec wrote: > > This patch attempts to enable automatic detection for RT kernels when no > > DT/ACPI cache information is available, by pre-allocating cacheinfo > > memory on the primary CPU. The allocated memory size depends on the > > number of cache leaves, which at that point is unknown without the > > DT/ACPI information. What this patch does is guess the number of cache > > leaves and pre-allocate memory on the primary CPU, then go back and > > reallocate the memory if the guess turns out to be wrong when automatic > > detection eventually runs on the secondary CPU. In that case, it will > > basically revert to the original behavior and still trigger a splat on > > RT kernels. The assumption is that most systems have identical CPUs, so > > the number of cache leaves will be the same on the secondary CPUs as the > > primary CPU. The "guess" uses the number of leaves of the primary CPU. > > Would it work to do the pre-allocation in fetch_cache_info() instead of > returning '-ENOENT' ? This would allow to not add a new step in > smp_prepare_cpus() and let all the logic in cacheinfo.c That was my initial intention, and I agree it would be much cleaner. Unfortunately, the number of cache leaves of the primary CPU hasn't been detected/populated at the time when fetch_cache_info() is called. That means we don't know how much memory to pre-allocate. This is the call flow that I recorded (read from top to bottom): smp_prepare_cpus init_cpu_topology parse_acpi_topology parse_dt_topology fetch_cache_info(cpu) init_of_cache_level(cpu) acpi_get_cache_info(cpu) allocate_cache_info(cpu) store_cpu_topology(this_cpu) update_siblings_masks detect_cache_attributes The number of cache leaves of the primary CPU is populated inside that last call to detect_cache_attributes(). If you can think of any other way around it, I am definitely open to suggestions. On a slightly different note, I think most of this code/mechanism is shared with RISC-V, but smp_prepare_cpus() is ARM64 specific. Unless we can think of a way to avoid that extra call to pre_alloc_cache_info(), we may need one for RISC-V as well. My main intention was to get some feedback and see if you are willing to accept something along these lines upstream. I can improve it and send subsequent versions of the patch if needed. Thanks again for taking the time to review it. Best regards, Radu _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel