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Tue, 30 Jun 2020 02:20:10 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 30 Jun 2020 02:20:09 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 30 Jun 2020 02:20:09 -0500 Received: from [127.0.0.1] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 05U7K7LH027187; Tue, 30 Jun 2020 02:20:08 -0500 Subject: Re: [PATCHv4 3/7] crypto: sa2ul: add sha1/sha256/sha512 support To: Herbert Xu References: <20200615071452.25141-1-t-kristo@ti.com> <20200615071452.25141-4-t-kristo@ti.com> <20200626043155.GA2683@gondor.apana.org.au> <2a89ea86-3b9e-06b5-fa8e-9dc6e5ad9aeb@ti.com> <20200630044936.GA22565@gondor.apana.org.au> From: Tero Kristo Message-ID: Date: Tue, 30 Jun 2020 10:20:06 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <20200630044936.GA22565@gondor.apana.org.au> Content-Language: en-US X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: j-keerthy@ti.com, davem@davemloft.net, linux-arm-kernel@lists.infradead.org, linux-crypto@vger.kernel.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 30/06/2020 07:49, Herbert Xu wrote: > On Fri, Jun 26, 2020 at 12:15:42PM +0300, Tero Kristo wrote: >> >> I have been experimenting with an alternate approach, where I have a small >> buffer within the context, this would be more like the way other drivers do >> this. If the buffer is closed before running out of space, I can push this >> to be processed by HW, otherwise I must fallback to SW. Does this sound like >> a better approach? > > You can buffer up to a block obviously. Anything beyond that > should just use a fallback. Only up-to block size? This would limit the buffer to 64-128 bytes. I was hoping I could cache data upto 1024 bytes at least in the context, as this would allow running certain openssl cases with hw accelerated crypto. Openssl speed test via cryptodev appears to do sha_init - sha_update - sha_final chain with any size data. -Tero -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel