From: Siddharth Vadapalli <s-vadapalli@ti.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: <bhelgaas@google.com>, <lpieralisi@kernel.org>, <kw@linux.com>,
<robh@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<conor+dt@kernel.org>, <linux-pci@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <vigneshr@ti.com>,
<afd@ti.com>, <srk@ti.com>, <s-vadapalli@ti.com>
Subject: Re: [PATCH 2/3] dt-bindings: PCI: ti,j721e-pci-*: Add checks for max-link-speed
Date: Wed, 17 Jan 2024 16:52:32 +0530 [thread overview]
Message-ID: <b8fb2e37-17c5-4af5-8e5d-b65a70c37734@ti.com> (raw)
In-Reply-To: <d8fba488-bdea-420b-84f2-a222315e1b81@linaro.org>
On 17/01/24 16:49, Krzysztof Kozlowski wrote:
> On 17/01/2024 12:15, Siddharth Vadapalli wrote:
>>
>>
>> On 17/01/24 16:30, Krzysztof Kozlowski wrote:
>>> On 17/01/2024 11:58, Siddharth Vadapalli wrote:
>>>> On 17/01/24 16:05, Krzysztof Kozlowski wrote:
>>>>> On 17/01/2024 11:25, Siddharth Vadapalli wrote:
>>>>>> Extend the existing compatible based checks for validating and enforcing
>>>>>> the "max-link-speed" property.
>>>>>
>>>>> Based on what? Driver or hardware? Your entire change suggests you
>>>>
>>>> Hardware. The PCIe controller on AM64 SoC supports up to Gen2 link speed while
>>>> the PCIe controllers on other SoCs support Gen3 link speed.
>>>>
>>>>> should just drop it from the binding, because this can be deduced from
>>>>> compatible.
>>>>
>>>> Could you please clarify? Isn't the addition of the checks for "max-link-speed"
>>>> identical to the checks which were added for "num-lanes", both of which are
>>>> Hardware specific?
>>>
>>> Compatible defines these values, at least what it looks like from the patch.
>>
>> In this patch, I have added checks for the "max-link-speed" property in the same
>> section that "num-lanes" is being evaluated.
>
> I know what you did in patch. I read it.
>
>> The values for "max-link-speed" are
>> based on the Hardware support and this patch is validating the "max-link-speed"
>> property in the device-tree nodes for the devices against the Hardware supported
>> values which this patch is adding in the corresponding section. Kindly let me
>> know if I misunderstood what you meant to convey.
>
> Nothing of this is relevant.
>
> I used two entirely different wordings for this and you still don't get
> it, so I don't know if I have third one.
>
> Maybe this:
> Move it to driver match data.
Ok. I will drop the checks for "max-link-speed" and move them to the driver. But
I wonder why the checks for "num-lanes" are needed in the first place when they
could be in the driver as well.
>
> So three entirely different wordings for the same. I don't have fourth...
>
> Best regards,
> Krzysztof
>
--
Regards,
Siddharth.
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next prev parent reply other threads:[~2024-01-17 11:23 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-17 10:25 [PATCH 0/3] Fix and update ti,j721e-pci-* bindings Siddharth Vadapalli
2024-01-17 10:25 ` [PATCH 1/3] dt-bindings: PCI: ti,j721e-pci-*: Fix check for num-lanes Siddharth Vadapalli
2024-01-17 10:34 ` Krzysztof Kozlowski
2024-01-17 10:47 ` Siddharth Vadapalli
2024-01-17 10:53 ` Krzysztof Kozlowski
2024-01-17 11:11 ` Siddharth Vadapalli
2024-01-17 11:17 ` Krzysztof Kozlowski
2024-01-17 10:25 ` [PATCH 2/3] dt-bindings: PCI: ti,j721e-pci-*: Add checks for max-link-speed Siddharth Vadapalli
2024-01-17 10:35 ` Krzysztof Kozlowski
2024-01-17 10:58 ` Siddharth Vadapalli
2024-01-17 11:00 ` Krzysztof Kozlowski
2024-01-17 11:15 ` Siddharth Vadapalli
2024-01-17 11:19 ` Krzysztof Kozlowski
2024-01-17 11:22 ` Siddharth Vadapalli [this message]
2024-01-17 11:34 ` Krzysztof Kozlowski
2024-01-17 10:25 ` [PATCH 3/3] dt-bindings: PCI: ti,j721e-pci-host: Add support for J722S SoC Siddharth Vadapalli
2024-01-17 10:36 ` Krzysztof Kozlowski
2024-01-17 11:24 ` Siddharth Vadapalli
2024-01-17 11:35 ` Krzysztof Kozlowski
2024-01-17 11:41 ` Siddharth Vadapalli
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