From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08BB4C4360F for ; Tue, 2 Apr 2019 19:14:49 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CCFFE2082C for ; Tue, 2 Apr 2019 19:14:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="WXYJN9HA" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CCFFE2082C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=8EN5v6Mz/zq3x4+0L5vrK6vToUXHwe9B3/CRuty9ZJM=; b=WXYJN9HAwTt8JOiOPCb+QmfBW yStCY+BOzKNZznxtOyRYRgfbIrR7vraebcxtB7tzxqrA601fDKcs6GcxVMOWJN/tMq9v207jTlrWN N8K/JiTUXcdWObdR6+IAIuMsVKxLY92o1cLAgarjpFBjSh8LLrKFGMdwaI5Cbac/poocrCUy/g7hF y5hoGpA77I664ZZt+uJaIwOMGe4qMBf9DNQnkRXdku4g/OSYkNxCY2V1Q88991PXzT4w2kJvaXeZ6 GRY04ZFQYJZ5kQM5rzDlaQnsJ7V5jkPc9y5rX2ysN4nPrneYnBYP2BacBptIvp/Ad3F7b3kJtJIVL QBqiewvZg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hBOrn-0001Sq-OD; Tue, 02 Apr 2019 19:14:39 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hBOrk-0001Rq-9e for linux-arm-kernel@lists.infradead.org; Tue, 02 Apr 2019 19:14:37 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9CA7680D; Tue, 2 Apr 2019 12:14:31 -0700 (PDT) Received: from [192.168.100.242] (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B1A773F68F; Tue, 2 Apr 2019 12:14:30 -0700 (PDT) Subject: Re: [PATCH 3/4] arm_pmu: acpi: spe: Add initial MADT/SPE probing To: John Garry , linux-arm-kernel@lists.infradead.org References: <20190326223938.5365-1-jeremy.linton@arm.com> <20190326223938.5365-4-jeremy.linton@arm.com> <2b53e957-6d36-fdfe-20e4-1664108c07ef@huawei.com> From: Jeremy Linton Message-ID: Date: Tue, 2 Apr 2019 14:14:29 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <2b53e957-6d36-fdfe-20e4-1664108c07ef@huawei.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190402_121436_351171_B774DF5D X-CRM114-Status: GOOD ( 24.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, lorenzo.pieralisi@arm.com, will.deacon@arm.com, sudeep.holla@arm.com, rjw@rjwysocki.net, linux-kernel@vger.kernel.org, linuxarm@huawei.com, linux-acpi@vger.kernel.org, james.morse@arm.com, catalin.marinas@arm.com, lenb@kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="windows-1252"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, First thanks for taking a look at this, second sorry about the delay... On 3/28/19 7:40 AM, John Garry wrote: > On 26/03/2019 22:39, Jeremy Linton wrote: >> ACPI 6.3 adds additional fields to the MADT GICC >> structure to describe SPE PPI's. We pick these out >> of the cached reference to the madt_gicc structure >> similarly to the core PMU code. We then create a platform >> device referring to the IRQ and let the user/module loader >> decide whether to load the SPE driver. >> >> Signed-off-by: Jeremy Linton >> --- >> =A0arch/arm64/include/asm/acpi.h |=A0 3 ++ >> =A0drivers/perf/arm_pmu_acpi.c=A0=A0 | 69 ++++++++++++++++++++++++++++++= +++++ >> =A02 files changed, 72 insertions(+) >> >> diff --git a/arch/arm64/include/asm/acpi.h = >> b/arch/arm64/include/asm/acpi.h >> index 7628efbe6c12..d10399b9f998 100644 >> --- a/arch/arm64/include/asm/acpi.h >> +++ b/arch/arm64/include/asm/acpi.h >> @@ -41,6 +41,9 @@ >> =A0=A0=A0=A0 (!(entry) || (entry)->header.length < ACPI_MADT_GICC_MIN_LE= NGTH || \ >> =A0=A0=A0=A0 (unsigned long)(entry) + (entry)->header.length > (end)) >> >> +#define ACPI_MADT_GICC_SPE=A0 (ACPI_OFFSET(struct = >> acpi_madt_generic_interrupt, \ >> +=A0=A0=A0 spe_interrupt) + sizeof(u16)) >> + >> =A0/* Basic configuration for ACPI */ >> =A0#ifdef=A0=A0=A0 CONFIG_ACPI >> =A0pgprot_t __acpi_get_mem_attribute(phys_addr_t addr); >> diff --git a/drivers/perf/arm_pmu_acpi.c b/drivers/perf/arm_pmu_acpi.c >> index 0f197516d708..a2418108eab2 100644 >> --- a/drivers/perf/arm_pmu_acpi.c >> +++ b/drivers/perf/arm_pmu_acpi.c >> @@ -74,6 +74,73 @@ static void arm_pmu_acpi_unregister_irq(int cpu) >> =A0=A0=A0=A0 acpi_unregister_gsi(gsi); >> =A0} >> >> +static struct resource spe_resources[] =3D { >> +=A0=A0=A0 { >> +=A0=A0=A0=A0=A0=A0=A0 /* irq */ >> +=A0=A0=A0=A0=A0=A0=A0 .flags=A0=A0=A0=A0=A0=A0=A0=A0=A0 =3D IORESOURCE_= IRQ, >> +=A0=A0=A0 } >> +}; >> + >> +static struct platform_device spe_dev =3D { >> +=A0=A0=A0 .name =3D "arm,spe-v1", >> +=A0=A0=A0 .id =3D -1, >> +=A0=A0=A0 .resource =3D spe_resources, >> +=A0=A0=A0 .num_resources =3D ARRAY_SIZE(spe_resources) >> +}; >> + >> +/* >> + * For lack of a better place, > = > It seems that the kernel Image size can now increase due to this part of = > SPE support even if ARM_SPE_PMU config is disabled. That is true, but it should be fairly small. > = > And I don't even think that ARM_SPE_PMU depends on ARM_PMU (which = > ARM_PMU_ACPI depends on). Well I don't think we want the generic SPE_PMU dependent on ACPI. So = this chunk of code could be wrapped in a SPE_PMU_ACPI block, and made = dependent on PMU_ACPI. OTOH, It seems a little trivial for that, and = maybe just tweaking the PMU_ACPI documentation to mention that it also = enables ACPI/SPE is a better plan. Opinions? > = > Thanks, > John > = > hook the normal PMU MADT walk >> + * and create a SPE device if we detect a recent MADT with >> + * a homogeneous PPI mapping. >> + */ >> +static int arm_spe_acpi_parse_irqs(void) >> +{ >> +=A0=A0=A0 int cpu, ret, irq; >> +=A0=A0=A0 int hetid; >> +=A0=A0=A0 u16 gsi =3D 0; >> +=A0=A0=A0 bool first =3D true; >> + >> +=A0=A0=A0 struct acpi_madt_generic_interrupt *gicc; >> + >> +=A0=A0=A0 /* >> +=A0=A0=A0=A0 * sanity check all the GICC tables for the same interrupt = number >> +=A0=A0=A0=A0 * for now we only support homogeneous ACPI/SPE machines. >> +=A0=A0=A0=A0 */ >> +=A0=A0=A0 for_each_possible_cpu(cpu) { >> +=A0=A0=A0=A0=A0=A0=A0 gicc =3D acpi_cpu_get_madt_gicc(cpu); >> + >> +=A0=A0=A0=A0=A0=A0=A0 if (gicc->header.length < ACPI_MADT_GICC_SPE) >> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 return -ENODEV; >> +=A0=A0=A0=A0=A0=A0=A0 if (first) { >> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 gsi =3D gicc->spe_interrupt; >> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 if (!gsi) >> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 return -ENODEV; >> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 hetid =3D find_acpi_cpu_topology_hete= ro_id(cpu); >> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 first =3D false; >> +=A0=A0=A0=A0=A0=A0=A0 } else if ((gsi !=3D gicc->spe_interrupt) || >> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 (hetid !=3D find_acpi_cpu_to= pology_hetero_id(cpu))) { >> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 pr_warn("ACPI: SPE must be homogeneou= s\n"); >> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 return -EINVAL; >> +=A0=A0=A0=A0=A0=A0=A0 } >> +=A0=A0=A0 } >> + >> +=A0=A0=A0 irq =3D acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE, >> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 ACPI_ACTIVE_HIGH); >> +=A0=A0=A0 if (irq < 0) { >> +=A0=A0=A0=A0=A0=A0=A0 pr_warn("ACPI: SPE Unable to register interrupt: = %d\n", gsi); >> +=A0=A0=A0=A0=A0=A0=A0 return irq; >> +=A0=A0=A0 } >> + >> +=A0=A0=A0 spe_resources[0].start =3D irq; >> +=A0=A0=A0 ret =3D platform_device_register(&spe_dev); >> +=A0=A0=A0 if (ret < 0) { >> +=A0=A0=A0=A0=A0=A0=A0 pr_warn("ACPI: SPE: Unable to register device\n"); >> +=A0=A0=A0=A0=A0=A0=A0 acpi_unregister_gsi(gsi); >> +=A0=A0=A0 } >> + >> +=A0=A0=A0 return ret; >> +} >> + >> =A0static int arm_pmu_acpi_parse_irqs(void) >> =A0{ >> =A0=A0=A0=A0 int irq, cpu, irq_cpu, err; >> @@ -279,6 +346,8 @@ static int arm_pmu_acpi_init(void) >> =A0=A0=A0=A0 if (acpi_disabled) >> =A0=A0=A0=A0=A0=A0=A0=A0 return 0; >> >> +=A0=A0=A0 arm_spe_acpi_parse_irqs(); /* failures are expected */ >> + >> =A0=A0=A0=A0 ret =3D arm_pmu_acpi_parse_irqs(); >> =A0=A0=A0=A0 if (ret) >> =A0=A0=A0=A0=A0=A0=A0=A0 return ret; >> > = > = _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel