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Wed, 28 Jan 2026 17:00:30 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface MIME-Version: 1.0 X-ThreadId: Agif6myIRndF Date: Wed, 28 Jan 2026 23:00:08 +0100 From: "Arnd Bergmann" To: =?UTF-8?Q?Stefan_D=C3=B6singer?= , linux-arm-kernel@lists.infradead.org Cc: soc@lists.linux.dev, "Linus Walleij" , "Jun Nie" , "Drew Fustini" Message-Id: In-Reply-To: <20260128203455.38569-1-stefandoesinger@gmail.com> References: <20260128203455.38569-1-stefandoesinger@gmail.com> Subject: Re: [RFC PATCH v2 0/7] Add support for ZTE zx297520v3 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260128_140039_010420_5250898D X-CRM114-Status: GOOD ( 21.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Jan 28, 2026, at 21:34, Stefan D=C3=B6singer wrote: > 4) The CPU is a Cortex A53 running in arm32 mode (in the shipped firmw= are=20 > too). It doesn't appear to have an FPU. Reading FPSID results in an=20 > exception (so vfpmodule.c/vfp_init says VFP is not available). I tried=20 > enabling p10 and p11 in NSACR, but without success. NSACR seems to alw= ays=20 > read 0 too. Is this really a Cortex A53 without FPU or did I miss=20 > something? I've never seen a Cortex-A53 without FPU and NEON, but since this is optional, it was a matter of time before we got one ;-) I assume that you were in EL3 when you tried to write to NSACR? >From EL2/EL1 it would still appear the same as not-implemented even if it is there but disabled in EL3. > 5) Relatedly, are there any advantages to running in arm64 mode? The=20 > devices are relatively memory constrained (64mb), so the larger binary=20 > size from 64 bit pointers is probably a negative, while the larger=20 > register set might be a positive. I doubt switching to arm64 mode is=20 > possible at all, but I'm nevertheless curious. Support for 64-bit cores is actually quite rudimentary in 32-bit more, as we are missing a lot of the errata workarounds and ARMv8 specific features in the kernel. If you can figure out how to use 64-bit kernel mode, that would be ideal. There is a noticeably higher memory usage even with 32-bit userspace though, so you'd lose several megabytes of memory as you said, and 64-bit userspace would be impossible since the aarch64 toolchain only supports hardfloat. You would also have to deal with a practical problem in OpenWRT, which as far as I know does not support building kernel and userland with different toolchains. > 6) The old removed zx29 code used "zte," as the vendor for the=20 > compatibles. Sanechips is a subsidiary of ZTE that designed these chip= s.=20 > Are there any preferences for either "zte," or "sanechips,"? I would stay with the previously used one Arnd