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Thu, 06 Feb 2020 12:41:27 +0000 MIME-Version: 1.0 Date: Thu, 06 Feb 2020 12:41:26 +0000 From: Marc Zyngier To: Will Deacon Subject: Re: [PATCH] arm64: ssbs: Fix context-switch when SSBS instructions are present In-Reply-To: <20200206122047.GA18762@willie-the-truck> References: <20200206113410.18301-1-will@kernel.org> <10b7b4b0bcc443db7028efbdee789549@kernel.org> <20200206122047.GA18762@willie-the-truck> Message-ID: X-Sender: maz@kernel.org User-Agent: Roundcube Webmail/1.3.8 X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: will@kernel.org, linux-arm-kernel@lists.infradead.org, mark.rutland@arm.com, kernel-team@android.com, stable@vger.kernel.org, catalin.marinas@arm.com, sramana@codeaurora.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200206_044129_429715_9F8AE360 X-CRM114-Status: GOOD ( 20.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, Srinivas Ramana , Catalin Marinas , stable@vger.kernel.org, kernel-team@android.com, linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2020-02-06 12:20, Will Deacon wrote: > On Thu, Feb 06, 2020 at 11:49:31AM +0000, Marc Zyngier wrote: >> On 2020-02-06 11:34, Will Deacon wrote: >> > When all CPUs in the system implement the SSBS instructions, we >> > advertise this via an HWCAP and allow EL0 to toggle the SSBS field >> > in PSTATE directly. Consequently, the state of the mitigation is not >> > accurately tracked by the TIF_SSBD thread flag and the PSTATE value >> > is authoritative. >> > >> > Avoid forcing the SSBS field in context-switch on such a system, and >> > simply rely on the PSTATE register instead. >> > >> > Cc: >> > Cc: Marc Zyngier >> > Cc: Catalin Marinas >> > Cc: Srinivas Ramana >> > Fixes: cbdf8a189a66 ("arm64: Force SSBS on context switch") >> > Signed-off-by: Will Deacon >> > --- >> > arch/arm64/kernel/process.c | 7 +++++++ >> > 1 file changed, 7 insertions(+) >> > >> > diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c >> > index d54586d5b031..45e867f40a7a 100644 >> > --- a/arch/arm64/kernel/process.c >> > +++ b/arch/arm64/kernel/process.c >> > @@ -466,6 +466,13 @@ static void ssbs_thread_switch(struct task_struct >> > *next) >> > if (unlikely(next->flags & PF_KTHREAD)) >> > return; >> > >> > + /* >> > + * If all CPUs implement the SSBS instructions, then we just >> > + * need to context-switch the PSTATE field. >> > + */ >> > + if (cpu_have_feature(cpu_feature(SSBS))) >> > + return; >> > + >> > /* If the mitigation is enabled, then we leave SSBS clear. */ >> > if ((arm64_get_ssbd_state() == ARM64_SSBD_FORCE_ENABLE) || >> > test_tsk_thread_flag(next, TIF_SSBD)) >> >> Looks goot to me. > > Ja! Ach... > >> Reviewed-by: Marc Zyngier > > Cheers. It occurs to me that, although the patch is correct, the > comment and > the commit message need tweaking because we're actually predicating > this on > the presence of SSBS in any form, so the instructions may not be > implemented. That's fine because the prctl() updates pstate, so it > remains > authoritative and can't be lost by one of the CPUs treating it as > RAZ/WI. True. It is the PSTATE bit that actually matters, not the presence of the control instruction. > I'll spin a v2 later on. Thanks, M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel