From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 596E7C3DA4D for ; Fri, 12 Jul 2024 07:07:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:Cc:To:Subject:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=AywRGY4ZtyurypgQoE/dzK5OakVFCcMMCy5xnckEWbg=; b=4qqsSDqKmv+upRUhYQo4gxifQj 5PgMOu0B2t93zPQiY5Mz+S7sqII+eQH4Oa6KYh4Wj7X6hOscoMZZJITFDwLCN01srEzP5Sos9u02D EnNKhP6ZTtS7MV8+3xx07rSQHATCQFRzW0982LpIPtJd3gYwleXsiqcYSD9XKj6clfdr5emuk41Ef 1ykN6PavXORF32e6ARfqvdSBHn5SeHluSGtAs5TFV/Bog8T0gYLnS4C8oG9NQvXbi+aeklExfgw7k IAi5Pa1rzgUGuC4p6MwW/9uYXFvJT/fGTC4ORkNYf6+Fd9ARDnjTwpYmv8oBbsRRaWbNORE9IAvJv c78O3e/Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sSAMu-0000000GiUb-1X4b; Fri, 12 Jul 2024 07:07:00 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sSAMb-0000000GiQL-0I30 for linux-arm-kernel@lists.infradead.org; Fri, 12 Jul 2024 07:06:43 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AE0461007; Fri, 12 Jul 2024 00:07:02 -0700 (PDT) Received: from [10.162.16.42] (a077893.blr.arm.com [10.162.16.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CBED73F762; Fri, 12 Jul 2024 00:06:34 -0700 (PDT) Message-ID: Date: Fri, 12 Jul 2024 12:36:31 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 02/12] arm64: Add PAR_EL1 field description To: Marc Zyngier , kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Joey Gouly References: <20240625133508.259829-1-maz@kernel.org> <20240625133508.259829-3-maz@kernel.org> Content-Language: en-US From: Anshuman Khandual In-Reply-To: <20240625133508.259829-3-maz@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240712_000641_189021_ED47B7F9 X-CRM114-Status: GOOD ( 15.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 6/25/24 19:05, Marc Zyngier wrote: > As KVM is about to grow a full emulation for the AT instructions, > add the layout of the PAR_EL1 register in its non-D128 configuration. Right, there are two variants for PAR_EL1 i.e D128 and non-D128. Probably it makes sense to define all these PAR_EL1 fields in arch/arm64/include/asm/sysreg.h, until arch/arm64/tools/sysreg evolves to accommodate different bit field layouts for the same register. > > Note that the constants are a bit ugly, as the register has two > layouts, based on the state of the F bit. Just wondering if it would be better to append 'VALID/INVALID' suffix for the fields to differentiate between when F = 0 and when F = 1 ? s/SYS_PAR_EL1_FST/SYS_PAR_INVALID_FST_EL1 s/SYS_PAR_EL1_SH/SYS_PAR_VALID_SH_EL1 Or something similar. > > Signed-off-by: Marc Zyngier > --- > arch/arm64/include/asm/sysreg.h | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index be41528194569..15c073359c9e9 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -325,7 +325,25 @@ > #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0) > > #define SYS_PAR_EL1_F BIT(0) > +/* When PAR_EL1.F == 1 */ > #define SYS_PAR_EL1_FST GENMASK(6, 1) > +#define SYS_PAR_EL1_PTW BIT(8) > +#define SYS_PAR_EL1_S BIT(9) > +#define SYS_PAR_EL1_AssuredOnly BIT(12) > +#define SYS_PAR_EL1_TopLevel BIT(13) > +#define SYS_PAR_EL1_Overlay BIT(14) > +#define SYS_PAR_EL1_DirtyBit BIT(15) > +#define SYS_PAR_EL1_F1_IMPDEF GENMASK_ULL(63, 48) > +#define SYS_PAR_EL1_F1_RES0 (BIT(7) | BIT(10) | GENMASK_ULL(47, 16)) > +#define SYS_PAR_EL1_RES1 BIT(11) > +/* When PAR_EL1.F == 0 */ > +#define SYS_PAR_EL1_SH GENMASK_ULL(8, 7) > +#define SYS_PAR_EL1_NS BIT(9) > +#define SYS_PAR_EL1_F0_IMPDEF BIT(10) > +#define SYS_PAR_EL1_NSE BIT(11) > +#define SYS_PAR_EL1_PA GENMASK_ULL(51, 12) > +#define SYS_PAR_EL1_ATTR GENMASK_ULL(63, 56) > +#define SYS_PAR_EL1_F0_RES0 (GENMASK_ULL(6, 1) | GENMASK_ULL(55, 52)) > > /*** Statistical Profiling Extension ***/ > #define PMSEVFR_EL1_RES0_IMP \