From: Matthias Brugger <matthias.bgg@gmail.com>
To: "irving.ch.lin" <irving-ch.lin@mediatek.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Ulf Hansson <ulf.hansson@linaro.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>
Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
Project_Global_Chrome_Upstream_Group@mediatek.com,
Qiqi Wang <qiqi.wang@mediatek.com>,
sirius.wang@mediatek.com, vince-wl.liu@mediatek.com,
jh.hsu@mediatek.com
Subject: Re: [PATCH 2/3] pmdomain: mediatek: Add bus protect control flow for MT8189
Date: Wed, 4 Feb 2026 18:46:03 +0100 [thread overview]
Message-ID: <ba86661d-3016-4205-8515-5e9ab2fa309b@gmail.com> (raw)
In-Reply-To: <20260202064820.347550-3-irving-ch.lin@mediatek.com>
On 02/02/2026 07:48, irving.ch.lin wrote:
> From: Irving-CH Lin <irving-ch.lin@mediatek.com>
>
> In MT8189 mminfra power domain, the bus protect policy separates
> into two parts, one is set before subsys clocks enabled, and another
> need to enable after subsys clocks enable.
>
> Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> ---
> drivers/pmdomain/mediatek/mtk-pm-domains.c | 31 ++++++++++++++++++----
> drivers/pmdomain/mediatek/mtk-pm-domains.h | 5 ++++
> 2 files changed, 31 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c
> index 0f0662676c07..3eeb0dabf7d7 100644
> --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c
> +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c
> @@ -250,7 +250,7 @@ static int scpsys_bus_protect_set(struct scpsys_domain *pd,
> MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
> }
>
> -static int scpsys_bus_protect_enable(struct scpsys_domain *pd)
> +static int scpsys_bus_protect_enable(struct scpsys_domain *pd, u8 flags)
> {
> for (int i = 0; i < SPM_MAX_BUS_PROT_DATA; i++) {
> const struct scpsys_bus_prot_data *bpd = &pd->data->bp_cfg[i];
> @@ -259,6 +259,10 @@ static int scpsys_bus_protect_enable(struct scpsys_domain *pd)
> if (!bpd->bus_prot_set_clr_mask)
> break;
>
> + if ((bpd->flags & BUS_PROT_IGNORE_SUBCLK) !=
> + (flags & BUS_PROT_IGNORE_SUBCLK))
> + continue;
> +
> if (bpd->flags & BUS_PROT_INVERTED)
> ret = scpsys_bus_protect_clear(pd, bpd);
> else
> @@ -270,7 +274,7 @@ static int scpsys_bus_protect_enable(struct scpsys_domain *pd)
> return 0;
> }
>
> -static int scpsys_bus_protect_disable(struct scpsys_domain *pd)
> +static int scpsys_bus_protect_disable(struct scpsys_domain *pd, u8 flags)
> {
> for (int i = SPM_MAX_BUS_PROT_DATA - 1; i >= 0; i--) {
> const struct scpsys_bus_prot_data *bpd = &pd->data->bp_cfg[i];
> @@ -279,6 +283,10 @@ static int scpsys_bus_protect_disable(struct scpsys_domain *pd)
> if (!bpd->bus_prot_set_clr_mask)
> continue;
>
> + if ((bpd->flags & BUS_PROT_IGNORE_SUBCLK) !=
> + (flags & BUS_PROT_IGNORE_SUBCLK))
> + continue;
> +
> if (bpd->flags & BUS_PROT_INVERTED)
> ret = scpsys_bus_protect_set(pd, bpd);
> else
> @@ -632,6 +640,15 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
> if (ret)
> goto err_pwr_ack;
>
> + /*
> + * In MT8189 mminfra power domain, the bus protect policy separates
> + * into two parts, one is set before subsys clocks enabled, and another
> + * need to enable after subsys clocks enable.
> + */
> + ret = scpsys_bus_protect_disable(pd, BUS_PROT_IGNORE_SUBCLK);
> + if (ret < 0)
> + goto err_pwr_ack;
> +
> /*
> * In few Mediatek platforms(e.g. MT6779), the bus protect policy is
> * stricter, which leads to bus protect release must be prior to bus
> @@ -648,7 +665,7 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
> if (ret < 0)
> goto err_disable_subsys_clks;
>
> - ret = scpsys_bus_protect_disable(pd);
> + ret = scpsys_bus_protect_disable(pd, 0);
> if (ret < 0)
> goto err_disable_sram;
>
> @@ -662,7 +679,7 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
> return 0;
>
> err_enable_bus_protect:
> - scpsys_bus_protect_enable(pd);
> + scpsys_bus_protect_enable(pd, 0);
> err_disable_sram:
> scpsys_sram_disable(pd);
> err_disable_subsys_clks:
> @@ -683,7 +700,7 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
> bool tmp;
> int ret;
>
> - ret = scpsys_bus_protect_enable(pd);
> + ret = scpsys_bus_protect_enable(pd, 0);
> if (ret < 0)
> return ret;
>
> @@ -697,6 +714,10 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
>
> clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks);
>
> + ret = scpsys_bus_protect_enable(pd, BUS_PROT_IGNORE_SUBCLK);
> + if (ret < 0)
> + return ret;
> +
> if (MTK_SCPD_CAPS(pd, MTK_SCPD_MODEM_PWRSEQ))
> scpsys_modem_pwrseq_off(pd);
> else
> diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.h b/drivers/pmdomain/mediatek/mtk-pm-domains.h
> index f608e6ec4744..a5dca24cbc2f 100644
> --- a/drivers/pmdomain/mediatek/mtk-pm-domains.h
> +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.h
> @@ -56,6 +56,7 @@ enum scpsys_bus_prot_flags {
> BUS_PROT_REG_UPDATE = BIT(1),
> BUS_PROT_IGNORE_CLR_ACK = BIT(2),
> BUS_PROT_INVERTED = BIT(3),
> + BUS_PROT_IGNORE_SUBCLK = BIT(4),
> };
>
> enum scpsys_bus_prot_block {
> @@ -95,6 +96,10 @@ enum scpsys_bus_prot_block {
> _BUS_PROT(_hwip, _mask, _set, _clr, _mask, _sta, \
> BUS_PROT_REG_UPDATE)
>
> +#define BUS_PROT_WR_IGN_SUBCLK(_hwip, _mask, _set, _clr, _sta) \
> + _BUS_PROT(_hwip, _mask, _set, _clr, _mask, _sta, \
> + BUS_PROT_IGNORE_CLR_ACK | BUS_PROT_IGNORE_SUBCLK)
> +
> #define BUS_PROT_INFRA_UPDATE_TOPAXI(_mask) \
> BUS_PROT_UPDATE(INFRA, _mask, \
> INFRA_TOPAXI_PROTECTEN, \
next prev parent reply other threads:[~2026-02-04 17:46 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-02 6:48 [PATCH 0/3] Add support for MT8189 power controller irving.ch.lin
2026-02-02 6:48 ` [PATCH 1/3] dt-bindings: power: Add MediaTek MT8189 power domain irving.ch.lin
2026-02-02 12:02 ` AngeloGioacchino Del Regno
2026-02-04 17:44 ` Matthias Brugger
2026-02-02 6:48 ` [PATCH 2/3] pmdomain: mediatek: Add bus protect control flow for MT8189 irving.ch.lin
2026-02-02 12:02 ` AngeloGioacchino Del Regno
2026-02-04 17:46 ` Matthias Brugger [this message]
2026-02-02 6:48 ` [PATCH 3/3] pmdomain: mediatek: Add power domain driver for MT8189 SoC irving.ch.lin
2026-02-02 12:02 ` AngeloGioacchino Del Regno
2026-02-04 17:47 ` Matthias Brugger
2026-02-02 14:59 ` [PATCH 0/3] Add support for MT8189 power controller Ulf Hansson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=ba86661d-3016-4205-8515-5e9ab2fa309b@gmail.com \
--to=matthias.bgg@gmail.com \
--cc=Project_Global_Chrome_Upstream_Group@mediatek.com \
--cc=angelogioacchino.delregno@collabora.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=irving-ch.lin@mediatek.com \
--cc=jh.hsu@mediatek.com \
--cc=krzk+dt@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=linux-pm@vger.kernel.org \
--cc=qiqi.wang@mediatek.com \
--cc=robh@kernel.org \
--cc=sirius.wang@mediatek.com \
--cc=ulf.hansson@linaro.org \
--cc=vince-wl.liu@mediatek.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox