From: <Codrin.Ciubotariu@microchip.com>
To: <Claudiu.Beznea@microchip.com>, <mturquette@baylibre.com>,
<sboyd@kernel.org>, <Nicolas.Ferre@microchip.com>,
<alexandre.belloni@bootlin.com>,
<Ludovic.Desroches@microchip.com>
Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, bbrezillon@kernel.org
Subject: Re: [PATCH 11/19] clk: at91: clk-generated: pass the id of changeable parent at registration
Date: Thu, 16 Jul 2020 16:57:18 +0000 [thread overview]
Message-ID: <bb3a3aac-c513-9f8c-975d-0bfddaa61bfc@microchip.com> (raw)
In-Reply-To: <1594812267-6697-12-git-send-email-claudiu.beznea@microchip.com>
Hi Claudiu,
On 15.07.2020 14:24, Claudiu Beznea wrote:
> Pass the ID of changeable parent at registration. This will allow
> the scalability of this clock driver with regards to the changeable
> parent ID for versions of this IP where changeable parent is not the
> last one in the parents list (e.g. SAMA7G5). In
> clk_generated_best_diff() the *best_diff variable is check against
> tmp_diff variable using ">=" operator instead of ">" so that in case
> the requested frequency could be obtained using fix parents + gck
> dividers but the clock also supports changeable parent to be able
> to force the usage of the changeable parent.
This is a great feature!
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
> drivers/clk/at91/clk-generated.c | 26 ++++++++++++++------------
> drivers/clk/at91/dt-compat.c | 8 +++++---
> drivers/clk/at91/pmc.h | 4 ++--
> drivers/clk/at91/sam9x60.c | 3 +--
> drivers/clk/at91/sama5d2.c | 31 +++++++++++++++----------------
> 5 files changed, 37 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c
> index 2448bdc63425..f9ca04c97128 100644
> --- a/drivers/clk/at91/clk-generated.c
> +++ b/drivers/clk/at91/clk-generated.c
> @@ -18,8 +18,6 @@
>
> #define GENERATED_MAX_DIV 255
>
> -#define GCK_INDEX_DT_AUDIO_PLL 5
> -
> struct clk_generated {
> struct clk_hw hw;
> struct regmap *regmap;
> @@ -29,7 +27,7 @@ struct clk_generated {
> u32 gckdiv;
> const struct clk_pcr_layout *layout;
> u8 parent_id;
> - bool audio_pll_allowed;
> + int chg_pid;
> };
>
> #define to_clk_generated(hw) \
> @@ -109,7 +107,7 @@ static void clk_generated_best_diff(struct clk_rate_request *req,
> tmp_rate = parent_rate / div;
> tmp_diff = abs(req->rate - tmp_rate);
>
> - if (*best_diff < 0 || *best_diff > tmp_diff) {
> + if (*best_diff < 0 || *best_diff >= tmp_diff) {
> *best_rate = tmp_rate;
> *best_diff = tmp_diff;
> req->best_parent_rate = parent_rate;
> @@ -129,7 +127,10 @@ static int clk_generated_determine_rate(struct clk_hw *hw,
> int i;
> u32 div;
>
> - for (i = 0; i < clk_hw_get_num_parents(hw) - 1; i++) {
> + for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
> + if (gck->chg_pid == i)
> + continue;
> +
One thing that the previous loop was preventing was to not allow other
gcks take clk_hw_get_num_parents(hw) - 1 as a parent. So the audio pll
(last one) was reserved for the gck of the audio peripherals only. With
this change, any peripheral can use chg_pid as a parent, preventing thus
its correct use by the peripherals that can actually need and change the
rate of chg_pid.
> parent = clk_hw_get_parent_by_index(hw, i);
> if (!parent)
> continue;
> @@ -161,10 +162,10 @@ static int clk_generated_determine_rate(struct clk_hw *hw,
> * that the only clks able to modify gck rate are those of audio IPs.
> */
The above comment should be updated.
>
> - if (!gck->audio_pll_allowed)
> + if (gck->chg_pid < 0)
> goto end;
Best regards,
Codrin
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-07-16 16:59 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-15 11:24 [PATCH 00/19] clk: at91: add sama7g5 clock support Claudiu Beznea
2020-07-15 11:24 ` [PATCH 01/19] clk: at91: clk-generated: continue if __clk_determine_rate() returns error Claudiu Beznea
2020-07-17 9:09 ` Alexandre Belloni
2020-07-15 11:24 ` [PATCH 02/19] clk: at91: clk-generated: check best_rate against ranges Claudiu Beznea
2020-07-17 9:10 ` Alexandre Belloni
2020-07-15 11:24 ` [PATCH 03/19] clk: at91: clk-sam9x60-pll: fix mul mask Claudiu Beznea
2020-07-17 9:11 ` Alexandre Belloni
2020-07-15 11:24 ` [PATCH 04/19] clk: at91: sam9x60-pll: use frac when computing pll frequency Claudiu Beznea
2020-07-15 11:24 ` [PATCH 05/19] clk: at91: sam9x60-pll: use logical or for range check Claudiu Beznea
2020-07-17 9:13 ` Alexandre Belloni
2020-07-15 11:24 ` [PATCH 06/19] clk: at91: sam9x60-pll: check fcore against ranges Claudiu Beznea
2020-07-17 9:23 ` Alexandre Belloni
2020-07-15 11:24 ` [PATCH 07/19] clk: at91: sam9x60-pll: use frac when setting frequency Claudiu Beznea
2020-07-17 9:12 ` Alexandre Belloni
2020-07-20 10:34 ` Claudiu.Beznea
2020-07-15 11:24 ` [PATCH 08/19] clk: at91: sam9x60: fix main rc oscillator frequency Claudiu Beznea
2020-07-17 9:17 ` Alexandre Belloni
2020-07-15 11:24 ` [PATCH 09/19] clk: at91: sckc: register slow_rc with accuracy option Claudiu Beznea
2020-07-15 15:39 ` Claudiu.Beznea
2020-07-15 11:24 ` [PATCH 10/19] clk: at91: replace conditional operator with double logical not Claudiu Beznea
2020-07-17 15:07 ` Alexandre Belloni
2020-07-20 10:36 ` Claudiu.Beznea
2020-07-15 11:24 ` [PATCH 11/19] clk: at91: clk-generated: pass the id of changeable parent at registration Claudiu Beznea
2020-07-16 16:57 ` Codrin.Ciubotariu [this message]
2020-07-15 11:24 ` [PATCH 12/19] clk: at91: clk-generated: add mux_table option Claudiu Beznea
2020-07-15 11:24 ` [PATCH 13/19] clk: at91: clk-master: add master clock support for SAMA7G5 Claudiu Beznea
2020-07-15 11:24 ` [PATCH 14/19] clk: at91: clk-peripheral: add support for changeable parent rate Claudiu Beznea
2020-07-15 11:24 ` [PATCH 15/19] clk: at91: clk-programmable: add mux_table option Claudiu Beznea
2020-07-15 11:24 ` [PATCH 16/19] clk: at91: add macro for pll ids mask Claudiu Beznea
2020-07-15 11:24 ` [PATCH 17/19] clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs Claudiu Beznea
2020-07-15 11:24 ` [PATCH 18/19] clk: at91: clk-utmi: add utmi support for sama7g5 Claudiu Beznea
2020-07-15 11:24 ` [PATCH 19/19] clk: at91: sama7g5: add clock " Claudiu Beznea
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=bb3a3aac-c513-9f8c-975d-0bfddaa61bfc@microchip.com \
--to=codrin.ciubotariu@microchip.com \
--cc=Claudiu.Beznea@microchip.com \
--cc=Ludovic.Desroches@microchip.com \
--cc=Nicolas.Ferre@microchip.com \
--cc=alexandre.belloni@bootlin.com \
--cc=bbrezillon@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mturquette@baylibre.com \
--cc=sboyd@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).