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Thu, 27 Feb 2020 16:53:33 +0000 MIME-Version: 1.0 Date: Thu, 27 Feb 2020 16:53:33 +0000 From: Marc Zyngier To: Ard Biesheuvel Subject: Re: [PATCH v4 0/5] ARM: decompressor: use by-VA cache maintenance for v7 cores In-Reply-To: References: <20200226165738.11201-1-ardb@kernel.org> <91023d8f118440439cf55847a6bc43c2@kernel.org> Message-ID: X-Sender: maz@kernel.org User-Agent: Roundcube Webmail/1.3.10 X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: ardb@kernel.org, linus.walleij@linaro.org, linux-arm-kernel@lists.infradead.org, linux-efi@vger.kernel.org, linux@armlinux.org.uk, nico@fluxnic.net, catalin.marinas@arm.com, tony@atomide.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200227_085335_631226_C96B724C X-CRM114-Status: GOOD ( 14.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-efi , Nicolas Pitre , Tony Lindgren , Catalin Marinas , Linus Walleij , Russell King , Linux ARM Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2020-02-27 16:47, Ard Biesheuvel wrote: > On Thu, 27 Feb 2020 at 17:01, Marc Zyngier wrote: >> >> On 2020-02-27 10:11, Linus Walleij wrote: >> > On Wed, Feb 26, 2020 at 5:57 PM Ard Biesheuvel wrote: >> > >> >> So instead, switch to the by-VA cache maintenance that the >> >> architecture >> >> requires for v7 and later (and ARM1176, as a side effect). >> >> >> >> Changes since v3: >> >> - ensure that the region that is cleaned after self-relocation of the >> >> zImage >> >> covers the appended DTB, if present >> >> >> >> Apologies to Linus, but due to this change, I decided not to take your >> >> Tested-by into account, and I would appreciate it if you could retest >> >> this version of the series? Thanks. >> > >> > No problem, I have tested it on the following: >> > >> > - ARMv7 Cortex A9 x 2 Qualcomm APQ8060 DragonBoard >> > - ARM PB11MPCore (4 x 1176) >> >> >> >> The ARM11MPCore isn't a bunch of 1176s glued together. It is actually >> a >> very >> different CPU, designed by a different team. >> >> >> > > It still takes the same code path in the cache routines, afaict: > - the architecture field in the main id register == 0xf, so it uses > __armv7_mmu_cache_flush > - ID_MMFR1[19:16] == 0x2, so it does not take the 'hierarchical' code > path which is modified by these patches Absolutely. From a SW perspective, this is treated in a similar way as ARM1176. The underlying HW is very different though... Thanks, M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel