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Tue, 01 Jun 2021 08:50:47 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 7FD6F10002A; Tue, 1 Jun 2021 08:50:46 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag2node3.st.com [10.75.127.6]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id C0C63208F2D; Tue, 1 Jun 2021 08:50:45 +0200 (CEST) Received: from lmecxl0912.lme.st.com (10.75.127.46) by SFHDAG2NODE3.st.com (10.75.127.6) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 1 Jun 2021 08:50:44 +0200 Subject: Re: [PATCH] ARM: dts: stm32: Rework LAN8710Ai PHY reset on DHCOM SoM To: Marek Vasut , CC: Alexandre Torgue , Patrice Chotard , Patrick Delaunay , References: <20210408230001.310215-1-marex@denx.de> From: Alexandre TORGUE Message-ID: Date: Tue, 1 Jun 2021 08:50:44 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210408230001.310215-1-marex@denx.de> Content-Language: en-US X-Originating-IP: [10.75.127.46] X-ClientProxiedBy: SFHDAG1NODE1.st.com (10.75.127.1) To SFHDAG2NODE3.st.com (10.75.127.6) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-01_03:2021-05-31, 2021-06-01 signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210531_235055_918826_2E75D959 X-CRM114-Status: GOOD ( 34.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 4/9/21 1:00 AM, Marek Vasut wrote: > The Microchip LAN8710Ai PHY requires XTAL1/CLKIN external clock to be > enabled when the nRST is toggled according to datasheet Microchip > LAN8710A/LAN8710Ai DS00002164B page 35 section 3.8.5.1 Hardware Reset: > " > A Hardware reset is asserted by driving the nRST input pin low. When > driven, nRST should be held low for the minimum time detailed in > Section 5.5.3, "Power-On nRST & Configuration Strap Timing," on page > 59 to ensure a proper transceiver reset. During a Hardware reset, an > external clock must be supplied to the XTAL1/CLKIN signal. > " > This is accidentally fulfilled in the current setup, where ETHCK_K is used > to supply both PHY XTAL1/CLKIN and is also fed back through eth_clk_fb to > supply ETHRX clock of the DWMAC. Hence, the DWMAC enables ETHRX clock, > that has ETHCK_K as parent, so ETHCK_K clock are also enabled, and then > the PHY reset toggles. > > However, this is not always the case, e.g. in case the PHY XTAL1/CLKIN > clock are supplied by some other clock source than ETHCK_K or in case > ETHRX clock are not supplied by ETHCK_K. In the later case, ETHCK_K would > be kept disabled, while ETHRX clock would be enabled, so the PHY would > not be receiving XTAL1/CLKIN clock and the reset would fail. > > Improve the DT by adding the PHY clock phandle into the PHY node, which > then also requires moving the PHY reset GPIO specifier in the same place > and that then also requires correct PHY reset GPIO timing, so add that > too. > > A brief note regarding the timing, the datasheet says the reset should > stay asserted for at least 100uS and software should wait at least 200nS > after deassertion. Set both delays to 500uS which should be plenty. > > Fixes: 34e0c7847dcf ("ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board") > Signed-off-by: Marek Vasut > Cc: Alexandre Torgue > Cc: Patrice Chotard > Cc: Patrick Delaunay > Cc: linux-stm32@st-md-mailman.stormreply.com > To: linux-arm-kernel@lists.infradead.org > --- > arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi > index 272a1a67a9ad..31d08423a32f 100644 > --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi > +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi > @@ -123,7 +123,6 @@ ðernet0 { > max-speed = <100>; > phy-handle = <&phy0>; > st,eth-ref-clk-sel; > - phy-reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; > > mdio0 { > #address-cells = <1>; > @@ -132,6 +131,13 @@ mdio0 { > > phy0: ethernet-phy@1 { > reg = <1>; > + /* LAN8710Ai */ > + compatible = "ethernet-phy-id0007.c0f0", > + "ethernet-phy-ieee802.3-c22"; > + clocks = <&rcc ETHCK_K>; > + reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; > + reset-assert-us = <500>; > + reset-deassert-us = <500>; > interrupt-parent = <&gpioi>; > interrupts = <11 IRQ_TYPE_LEVEL_LOW>; > }; > Applied on stm32-next. Thanks. Alex _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel