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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8434ad03fdcsm15269159b3a.24.2026.06.17.03.37.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 17 Jun 2026 03:37:37 -0700 (PDT) Message-ID: Date: Wed, 17 Jun 2026 18:37:33 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 5/6] drm/verisilicon: add DCUltraLite chip identity to HWDB To: Icenowy Zheng , maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260615065003.76661-1-a0987203069@gmail.com> <20260615065003.76661-6-a0987203069@gmail.com> <62c0b8ab9b6d9f994daa8bb60b3b626688af7d5e.camel@iscas.ac.cn> Content-Language: en-US From: Joey Lu In-Reply-To: <62c0b8ab9b6d9f994daa8bb60b3b626688af7d5e.camel@iscas.ac.cn> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260617_033738_601938_CF176189 X-CRM114-Status: GOOD ( 19.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 6/15/2026 4:57 PM, Icenowy Zheng wrote: > 在 2026-06-15一的 14:50 +0800，Joey Lu写道： >> Register the Nuvoton MA35D1 DCUltraLite chip identity in >> vs_chip_identities[]: >>   model       = 0x0   (DCUltraLite; Verisilicon uses 0 for this IP) >>   revision    = 0x5560 >>   customer_id = 0x305 >>   generation  = VSDC_GEN_DC8000 >>   display_count = 1 >>   max_cursor_size = 32 > I suggest make this more human-readable instead of replicating the > machine-readable data of HWDB. > > My proposal here: > > ``` > The Nuvoton MA35D1 chip contains a DCUltraLite display controller with > model number 0x0 (sic, the model name contains no number either), > revision 0x5560 and customer ID 0x305. It has a similar register map > with DC8000, only one display output and only 32x32 cursor supported. > ``` Thanks. I will use your proposed wording for the commit message in v5 >> Placing this entry last makes it the gate that enables MA35D1 >> hardware >> recognition only after all the supporting ops and DT binding changes >> are >> in place. > It's a little ambiguous that "last" here means whether the last in the > patchset or the last in the HWDB array, although I think it's not so > needed to explain the reason of the place in the patchset. > > I propose just say `Adding it to the HWDB to enable it to be usable > with the verisilicon driver.` . I will simplify the placement sentence to "Adding it to the HWDB to enable it to be usable with the verisilicon driver." in v5. >> Signed-off-by: Joey Lu >> --- >>  drivers/gpu/drm/verisilicon/vs_hwdb.c | 10 ++++++++++ >>  1 file changed, 10 insertions(+) >> >> diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.c >> b/drivers/gpu/drm/verisilicon/vs_hwdb.c >> index 91524d16f778..7d630a667a3f 100644 >> --- a/drivers/gpu/drm/verisilicon/vs_hwdb.c >> +++ b/drivers/gpu/drm/verisilicon/vs_hwdb.c >> @@ -129,6 +129,16 @@ static struct vs_chip_identity >> vs_chip_identities[] = { >>   .max_cursor_size = 64, >>   .formats = &vs_formats_no_yuv444, >>   }, >> + { >> + .model = 0x0, /* DCUltraLite */ >> + .revision = 0x5560, >> + .customer_id = 0x305, >> + >> + .generation = VSDC_GEN_DC8000, >> + .display_count = 1, >> + .max_cursor_size = 32, >> + .formats = &vs_formats_no_yuv444, >> + }, >>  }; >> >>  int vs_fill_chip_identity(struct regmap *regs,