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Tue, 03 Feb 2026 03:19:00 -0800 (PST) Received: from [192.168.88.32] ([150.228.93.21]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-482dbc7f580sm149384895e9.2.2026.02.03.03.18.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Feb 2026 03:19:00 -0800 (PST) Message-ID: Date: Tue, 3 Feb 2026 12:18:54 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 0/3] s32g: Use a syscon for GPR To: Dan Carpenter , Chester Lin Cc: Alexandre Torgue , Andrew Lunn , Conor Dooley , "David S. Miller" , devicetree@vger.kernel.org, Eric Dumazet , Fabio Estevam , Frank Li , Ghennadi Procopciuc , imx@lists.linux.dev, Jakub Kicinski , Jan Petrous , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, Matthias Brugger , Maxime Coquelin , netdev@vger.kernel.org, NXP S32 Linux Team , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , linaro-s32@linaro.org References: From: Paolo Abeni In-Reply-To: X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: PPwfrNgHbVu4Mc_jQe7oRh2DnI-pONePxbgtI09C9Tk_1770117541 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260203_031906_737707_61101AF4 X-CRM114-Status: GOOD ( 28.22 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 1/30/26 2:19 PM, Dan Carpenter wrote: > The s32g devices have a GPR register region which holds a number of > miscellaneous registers. Currently only the stmmac/dwmac-s32.c uses > anything from there and we just add a line to the device tree to > access that GMAC_0_CTRL_STS register: > > reg = <0x4033c000 0x2000>, /* gmac IP */ > <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ > > I have included the whole list of registers below. > > We still have to maintain backwards compatibility to this format, > of course, but it would be better to access these registers through a > syscon. Putting all the registers together is more organized and shows > how the hardware actually is implemented. > > Secondly, in some versions of this chipset those registers can only be > accessed via SCMI. It's relatively straight forward to handle this > by writing a syscon driver and registering it with of_syscon_register_regmap() > but it's complicated to deal with if the registers aren't grouped > together. > > Changes since v5: > * Fix O vs 0 typo in yaml file > * Add Jan Petrous's Reviewed-by tag > > Changes since v4: > * Return an error if regmap_write() fails > * Add Rob's Reviewed-by tag to the yaml patch > > Changes since v3: > * Fix the yaml file format > * Add netdev to the CC list on all emails so the CI triggers > > Changes since v2: > * Improve the documentation in .../bindings/net/nxp,s32-dwmac.yaml > * "[PATCH v2 2/4] dt-bindings: mfd: syscon: Document the GPR syscon > for the NXP S32 SoCs" was applied so drop it. > > Changes since v1: > * Add imx@lists.linux.dev to the CC list. > * Fix forward porting bug. s/PHY_INTF_SEL_RGMII/S32_PHY_INTF_SEL_RGMII/ > * Use the correct SoC names nxp,s32g2-gpr and nxp,s32g3-gpr instead of > nxp,s32g-gpr which is the SoC family. > * Fix the phandle name by adding the vendor prefix > * Fix the documentation for the phandle > * Remove #address-cells and #size-cells from the syscon block > > Here is the whole list of registers in the GPR region > > Starting from 0x4007C000 > > 0 Software-Triggered Faults (SW_NCF) > 4 GMAC Control (GMAC_0_CTRL_STS) > 28 CMU Status 1 (CMU_STATUS_REG1) > 2C CMUs Status 2 (CMU_STATUS_REG2) > 30 FCCU EOUT Override Clear (FCCU_EOUT_OVERRIDE_CLEAR_REG) > 38 SRC POR Control (SRC_POR_CTRL_REG) > 54 GPR21 (GPR21) > 5C GPR23 (GPR23) > 60 GPR24 Register (GPR24) > CC Debug Control (DEBUG_CONTROL) > F0 Timestamp Control (TIMESTAMP_CONTROL_REGISTER) > F4 FlexRay OS Tick Input Select (FLEXRAY_OS_TICK_INPUT_SELECT_REG) > FC GPR63 Register (GPR63) > > Starting from 0x4007CA00 > > 0 Coherency Enable for PFE Ports (PFE_COH_EN) > 4 PFE EMAC Interface Mode (PFE_EMACX_INTF_SEL) > 20 PFE EMACX Power Control (PFE_PWR_CTRL) > 28 Error Injection on Cortex-M7 AHB and AXI Pipe (CM7_TCM_AHB_SLICE) > 2C Error Injection AHBP Gasket Cortex-M7 (ERROR_INJECTION_AHBP_GASKET_CM7) > 40 LLCE Subsystem Status (LLCE_STAT) > 44 LLCE Power Control (LLCE_CTRL) > 48 DDR Urgent Control (DDR_URGENT_CTRL) > 4C FTM Global Load Control (FLXTIM_CTRL) > 50 FTM LDOK Status (FLXTIM_STAT) > 54 Top CMU Status (CMU_STAT) > 58 Accelerator NoC No Pending Trans Status (NOC_NOPEND_TRANS) > 90 SerDes RD/WD Toggle Control (PCIE_TOGGLE) > 94 SerDes Toggle Done Status (PCIE_TOGGLEDONE_STAT) > E0 Generic Control 0 (GENCTRL0) > E4 Generic Control 1 (GENCTRL1) > F0 Generic Status 0 (GENSTAT0) > FC Cortex-M7 AXI Parity Error and AHBP Gasket Error Alarm (CM7_AXI_AHBP_GASKET_ERROR_ALARM) > > Starting from 4007C800 > > 4 GPR01 Register (GPR01) > 30 GPR12 Register (GPR12) > 58 GPR22 Register (GPR22) > 70 GPR28 Register (GPR28) > 74 GPR29 Register (GPR29) > > Starting from 4007CB00 > > 4 WKUP Pad Pullup/Pulldown Select (WKUP_PUS) > > Dan Carpenter (3): > net: stmmac: s32: use a syscon for S32_PHY_INTF_SEL_RGMII > dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon > dts: s32g: Add GPR syscon region It looks like patch 3/3 depends on 1/3 but it should land in a different tree, as patches 1 && 2 looks suitable for 'net-next' and 3/3 should probably go via the arm/freescale tree. We either need explicit ack from freescale maintainers or this should be split across subtrees, right? Thanks, Paolo