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Wed, 9 Jul 2025 23:00:34 -0700 From: Nicolin Chen To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v9 27/29] iommu/tegra241-cmdqv: Do not statically map LVCMDQs Date: Wed, 9 Jul 2025 22:59:19 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB76:EE_|DS7PR12MB8418:EE_ X-MS-Office365-Filtering-Correlation-Id: 4da18181-12c8-4a76-0f2d-08ddbf772434 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Wgiiq8ewBJC0tSNvg0jldor7oA4j3EMLoNGi5sM9GYrCl38JxROiZ2bZcTGH?= =?us-ascii?Q?1D57tGQE3oPp0nbbcg2L1BvPsTFixP0DTS0jlbeG1wSKjShAwndr3RbdQu3N?= =?us-ascii?Q?1hxlq5enqBfGlBj/zeai0CYc4vrZRdGiJPfg1wTj4UjiehKTgFEtuIgQ7glA?= =?us-ascii?Q?FqFuhaQp2jatPim0fvKOdOuPzvhVZ1oMm8EPdNFF8m0taG5H335WT/9SEnuO?= =?us-ascii?Q?ww6M1oC1JYIkKY3dQsNTlxZ9R0snWmv2pmE/G4JmT5e0XoQC1j6z+ZovnujD?= =?us-ascii?Q?9vw/aYe3oDVfEEvsoCbRwuz9wDd91JSVbxy6gNRLUglhVy3BgU1ojfEKbKm1?= =?us-ascii?Q?TS7PR/8aXXnvHJ7wz0wmXDjwa7wLPWPlmmIEvJ54dVnzEop4kjde747IjqUl?= =?us-ascii?Q?m5DNXZUCPDoKCzzRxzl+f+rHvJ0VuB/2lL672nJANK7dfPFwjoXw3wZmkgto?= =?us-ascii?Q?ZWC917V8d6pJociH1ZYUv9clIpH3shoPqCZcK2yvaDGtcquMgdk4ujCGSW9A?= =?us-ascii?Q?5Bt7A5GYa5/E81Q7+UFkWwUhi3npdmXrID1kEBkwsmkoZUrbBHdkFkH+ecNt?= =?us-ascii?Q?ij4xj8MjeexYIIq9OCelXr9YxjNJ80t4Ln9jcR+Xp6azCD05TmKZ4fpNDp1c?= =?us-ascii?Q?5/7gq2jQZ6UnTIv6tSVH1R9RENufA2hLXKEPnG8EQNJddvvdDld9ob13kbRB?= =?us-ascii?Q?eIOzBhEQPKERVgSohgyadmsCALW9DDfJz2WiDiXL1L8CpXpcKLfEtMBwYPB2?= =?us-ascii?Q?hBNK5M3KrmQPtDaekrYyIv/t2/KxhyIx2k5H/hqICZPi32O7EAQ28h/9hFwT?= =?us-ascii?Q?OPz1fqnma5mCa2W5L4DoU3gT1zJn2dwql7MAi1pCOCTsuGw11CJsrfWPClG0?= =?us-ascii?Q?IWB3veGrDUzcdLS97D+9wsOPYbH/q2tPon5TBLxuvWIqjMAnwd5wV5R4oVV/?= =?us-ascii?Q?SoWVyICeelJsWrj6q//001Qzcnl/mGM2afMGJahE9S5Aj0xwyZS1UFxIS4ZR?= =?us-ascii?Q?xy1b1DlsFUesz0Bb0pGIqV5neUzdRrEX8fqEQsdx9WrceJyzv0ZaY0D/jrZf?= =?us-ascii?Q?y4tTafotr6sZ0en3iKhiTAH1ZxFRNudHgx1XhfBr1v2eQCjoF91Ex7jJYfZJ?= =?us-ascii?Q?YBz6scOQZ27pwTxq/QYH4fvrDOgKUQiqaPxTayKZTEjJ4UKKFyfd2pu4g80S?= =?us-ascii?Q?DqI1sj4yWNQy6Iqvxd9WhiwvCKq81yxSrAmkctAk0el1Ct7OTI8LWAPAMQy5?= =?us-ascii?Q?077qfkqxcy5/vztq5aXhaL9wHzZdwPsETl0Y8r2NaxdfAm0KEjhESFABF+61?= =?us-ascii?Q?HBpmsLQhrzEkNzNKVsqD9L9hipLKKAJ5jI2k+9etpxlW8+FpJHwGn3vqD1Zg?= =?us-ascii?Q?6V5of5ceik22tWEAf+kVUUbqJkyGfxhvQVYccdPF/X6F4haep5GNpimLZ4ap?= =?us-ascii?Q?HBIESGzvp7GwW8NyYWbBjEDi1TDN4acIHoF1t8PjO1/5MYI8tk1x1L+x7UZ7?= =?us-ascii?Q?6vxthNxNQxkfQxaG6odWqA1GMmM8h4xgOI9h?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(7416014)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jul 2025 06:00:58.4090 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4da18181-12c8-4a76-0f2d-08ddbf772434 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB76.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8418 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250709_230103_035217_7E64EB84 X-CRM114-Status: GOOD ( 15.83 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org To simplify the mappings from global VCMDQs to VINTFs' LVCMDQs, the design chose to do static allocations and mappings in the global reset function. However, with the user-owned VINTF support, it exposes a security concern: if user space VM only wants one LVCMDQ for a VINTF, statically mapping two or more LVCMDQs creates a hidden VCMDQ that user space could DoS attack by writing random stuff to overwhelm the kernel with unhandleable IRQs. Thus, to support the user-owned VINTF feature, a LVCMDQ mapping has to be done dynamically. HW allows pre-assigning global VCMDQs in the CMDQ_ALLOC registers, without finalizing the mappings by keeping CMDQV_CMDQ_ALLOCATED=0. So, add a pair of map/unmap helper that simply sets/clears that bit. For kernel-owned VINTF0, move LVCMDQ mappings to tegra241_vintf_hw_init(), and the unmappings to tegra241_vintf_hw_deinit(). For user-owned VINTFs that will be added, the mappings/unmappings will be on demand upon an LVCMDQ allocation from the user space. However, the dynamic LVCMDQ mapping/unmapping can complicate the timing of calling tegra241_vcmdq_hw_init/deinit(), which write LVCMDQ address space, i.e. requiring LVCMDQ to be mapped. Highlight that with a note to the top of either of them. Acked-by: Pranjal Shrivastava Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- .../iommu/arm/arm-smmu-v3/tegra241-cmdqv.c | 37 +++++++++++++++++-- 1 file changed, 33 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c index 8d418c131b1b..869c90b660c1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c +++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c @@ -351,6 +351,7 @@ tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu, /* HW Reset Functions */ +/* This function is for LVCMDQ, so @vcmdq must not be unmapped yet */ static void tegra241_vcmdq_hw_deinit(struct tegra241_vcmdq *vcmdq) { char header[64], *h = lvcmdq_error_header(vcmdq, header, 64); @@ -379,6 +380,7 @@ static void tegra241_vcmdq_hw_deinit(struct tegra241_vcmdq *vcmdq) dev_dbg(vcmdq->cmdqv->dev, "%sdeinited\n", h); } +/* This function is for LVCMDQ, so @vcmdq must be mapped prior */ static int tegra241_vcmdq_hw_init(struct tegra241_vcmdq *vcmdq) { char header[64], *h = lvcmdq_error_header(vcmdq, header, 64); @@ -404,16 +406,42 @@ static int tegra241_vcmdq_hw_init(struct tegra241_vcmdq *vcmdq) return 0; } +/* Unmap a global VCMDQ from the pre-assigned LVCMDQ */ +static void tegra241_vcmdq_unmap_lvcmdq(struct tegra241_vcmdq *vcmdq) +{ + u32 regval = readl(REG_CMDQV(vcmdq->cmdqv, CMDQ_ALLOC(vcmdq->idx))); + char header[64], *h = lvcmdq_error_header(vcmdq, header, 64); + + writel(regval & ~CMDQV_CMDQ_ALLOCATED, + REG_CMDQV(vcmdq->cmdqv, CMDQ_ALLOC(vcmdq->idx))); + dev_dbg(vcmdq->cmdqv->dev, "%sunmapped\n", h); +} + static void tegra241_vintf_hw_deinit(struct tegra241_vintf *vintf) { - u16 lidx; + u16 lidx = vintf->cmdqv->num_lvcmdqs_per_vintf; - for (lidx = 0; lidx < vintf->cmdqv->num_lvcmdqs_per_vintf; lidx++) - if (vintf->lvcmdqs && vintf->lvcmdqs[lidx]) + /* HW requires to unmap LVCMDQs in descending order */ + while (lidx--) { + if (vintf->lvcmdqs && vintf->lvcmdqs[lidx]) { tegra241_vcmdq_hw_deinit(vintf->lvcmdqs[lidx]); + tegra241_vcmdq_unmap_lvcmdq(vintf->lvcmdqs[lidx]); + } + } vintf_write_config(vintf, 0); } +/* Map a global VCMDQ to the pre-assigned LVCMDQ */ +static void tegra241_vcmdq_map_lvcmdq(struct tegra241_vcmdq *vcmdq) +{ + u32 regval = readl(REG_CMDQV(vcmdq->cmdqv, CMDQ_ALLOC(vcmdq->idx))); + char header[64], *h = lvcmdq_error_header(vcmdq, header, 64); + + writel(regval | CMDQV_CMDQ_ALLOCATED, + REG_CMDQV(vcmdq->cmdqv, CMDQ_ALLOC(vcmdq->idx))); + dev_dbg(vcmdq->cmdqv->dev, "%smapped\n", h); +} + static int tegra241_vintf_hw_init(struct tegra241_vintf *vintf, bool hyp_own) { u32 regval; @@ -441,8 +469,10 @@ static int tegra241_vintf_hw_init(struct tegra241_vintf *vintf, bool hyp_own) */ vintf->hyp_own = !!(VINTF_HYP_OWN & readl(REG_VINTF(vintf, CONFIG))); + /* HW requires to map LVCMDQs in ascending order */ for (lidx = 0; lidx < vintf->cmdqv->num_lvcmdqs_per_vintf; lidx++) { if (vintf->lvcmdqs && vintf->lvcmdqs[lidx]) { + tegra241_vcmdq_map_lvcmdq(vintf->lvcmdqs[lidx]); ret = tegra241_vcmdq_hw_init(vintf->lvcmdqs[lidx]); if (ret) { tegra241_vintf_hw_deinit(vintf); @@ -476,7 +506,6 @@ static int tegra241_cmdqv_hw_reset(struct arm_smmu_device *smmu) for (lidx = 0; lidx < cmdqv->num_lvcmdqs_per_vintf; lidx++) { regval = FIELD_PREP(CMDQV_CMDQ_ALLOC_VINTF, idx); regval |= FIELD_PREP(CMDQV_CMDQ_ALLOC_LVCMDQ, lidx); - regval |= CMDQV_CMDQ_ALLOCATED; writel_relaxed(regval, REG_CMDQV(cmdqv, CMDQ_ALLOC(qidx++))); } -- 2.43.0