Re: [PATCH 18/19] arm64: dts: qcom: add initial support for QCS8300 DTSI

[Krzysztof Kozlowski <krzk@kernel.org>]

On 04/09/2024 10:33, Jingyi Wang wrote:
> Add initial DTSI for QCS8300 SoC.
> 
> This revision brings support for:
> - CPUs with cpu idle
> - interrupt-controller with PDC wakeup support
> - gcc
> - TLMM
> - interconnect
> - qup with uart
> - smmu
> - pmic
> - ufs
> - ipcc
> - sram
> - remoteprocs including ADSP,CDSP and GPDSP
> 
> [Zhenhua: added the smmu node]
> Co-developed-by: Zhenhua Huang <quic_zhenhuah@quicinc.com>
> Signed-off-by: Zhenhua Huang <quic_zhenhuah@quicinc.com>
> [Xin: added ufs/adsp/gpdsp nodes]
> Co-developed-by: Xin Liu <quic_liuxin@quicinc.com>
> Signed-off-by: Xin Liu <quic_liuxin@quicinc.com>
> [Kyle: added the aoss_qmp node]
> Co-developed-by: Kyle Deng <quic_chunkaid@quicinc.com>
> Signed-off-by: Kyle Deng <quic_chunkaid@quicinc.com>
> [Tingguo: added the pmic nodes]
> Co-developed-by: Tingguo Cheng <quic_tingguoc@quicinc.com>
> Signed-off-by: Tingguo Cheng <quic_tingguoc@quicinc.com>
> [Raviteja: added interconnect nodes]
> Co-developed-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs8300.dtsi | 1282 +++++++++++++++++++++++++++++++++
>  1 file changed, 1282 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> new file mode 100644
> index 000000000000..244fa8bf97d9
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> @@ -0,0 +1,1282 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <dt-bindings/clock/qcom,qcs8300-gcc.h>
> +#include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/interconnect/qcom,icc.h>
> +#include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/mailbox/qcom-ipcc.h>
> +#include <dt-bindings/power/qcom,rpmhpd.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +
> +/ {
> +	interrupt-parent = <&intc>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	clocks {
> +		sleep_clk: sleep-clk {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <32000>;

Are you sure that sleep clock is physically part of the SoC?

> +		};
> +	};
> +
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +

...

> +
> +	soc: soc@0 {
> +		compatible = "simple-bus";
> +
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges = <0 0 0 0 0x10 0>;

ranges follow compatible, so it is the second property.



Best regards,
Krzysztof