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X-CSE-ConnectionGUID: mGolnRH3T5a9IGpSC6mVKg== X-CSE-MsgGUID: vQhxW/evSVObE4ol3snx/g== X-IronPort-AV: E=McAfee;i="6800,10657,11603"; a="64550602" X-IronPort-AV: E=Sophos;i="6.19,281,1754982000"; d="scan'208";a="64550602" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Nov 2025 02:43:21 -0800 X-CSE-ConnectionGUID: Isd4eBPLRcKDgK5YT6ErMw== X-CSE-MsgGUID: OiLDIX16S4G9aa1KuMyt+A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,281,1754982000"; d="scan'208";a="218203072" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.252]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Nov 2025 02:43:12 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Date: Wed, 5 Nov 2025 12:43:09 +0200 (EET) To: Niklas Cassel cc: Vincent Guittot , Bjorn Helgaas , chester62515@gmail.com, mbrugger@suse.com, ghennadi.procopciuc@oss.nxp.com, s32@nxp.com, bhelgaas@google.com, jingoohan1@gmail.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, Ionut.Vicovan@nxp.com, larisa.grigore@nxp.com, Ghennadi.Procopciuc@nxp.com, ciprianmarian.costea@nxp.com, bogdan.hamciuc@nxp.com, Frank.li@nxp.com, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, LKML , imx@lists.linux.dev Subject: Re: [PATCH 3/4 v3] PCI: s32g: Add initial PCIe support (RC) In-Reply-To: Message-ID: References: <20251022174309.1180931-4-vincent.guittot@linaro.org> <20251022190402.GA1262472@bhelgaas> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251105_024323_452323_BBABFE6B X-CRM114-Status: GOOD ( 17.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 5 Nov 2025, Niklas Cassel wrote: > On Fri, Oct 24, 2025 at 08:50:46AM +0200, Vincent Guittot wrote: > > On Wed, 22 Oct 2025 at 21:04, Bjorn Helgaas wrote: > > > > + dw_pcie_dbi_ro_wr_en(pci); > > > > + > > > > + val = dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE); > > > > + val |= PORT_FORCE_DO_DESKEW_FOR_SRIS; > > > > + dw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val); > > > > + > > > > + /* > > > > + * Set max payload supported, 256 bytes and > > > > + * relaxed ordering. > > > > + */ > > > > + val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); > > > > + val &= ~(PCI_EXP_DEVCTL_RELAX_EN | > > > > + PCI_EXP_DEVCTL_PAYLOAD | > > > > + PCI_EXP_DEVCTL_READRQ); > > > > + val |= PCI_EXP_DEVCTL_RELAX_EN | > > > > + PCI_EXP_DEVCTL_PAYLOAD_256B | > > > > + PCI_EXP_DEVCTL_READRQ_256B; > > > > + dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val); > > > > > > MPS and relaxed ordering should be configured by the PCI core. Is > > > there some s32g-specific restriction about these? > > > > I will check with the team why they did that > > Most likely, the reason is that, the PCI core does not set the MPS to the > maximum supported MPS for the root port. PCI core set/doesn't set MPS based on config. Perhaps try with CONFIG_PCIE_BUS_PERFORMANCE. > So without that change, the port will use use 128B instead of 256B. > > I assume that you should be able to drop (at least the MPS part) if this > change gets accepted: > https://lore.kernel.org/linux-pci/20251104165125.174168-1-18255117159@163.com/ > > > Kind regards, > Niklas > -- i.