[PATCH 0/5] Add ethernet support for RPi5

[PATCH 0/5] Add ethernet support for RPi5

[Stanimir Varbanov]

Hello,

Few patches to enable support of ethernet on RPi5.

 - first patch is setting upper 32bits of DMA RX ring buffer in case of
   RX queue corruption.
 - second patch is adding a new compatible in cdns,macb yaml document
 - third patch adds compatible and configuration for raspberrypi,rp1-gem
 - forth and fifth patches are adding and enabling ethernet DT node on
   RPi5.

Comments are welcome!

Regards,
~Stan

Dave Stevenson (2):
  dt-bindings: net: cdns,macb: Add compatible for Raspberry Pi RP1
  net: cadence: macb: Add support for Raspberry Pi RP1 ethernet
    controller

Stanimir Varbanov (3):
  net: cadence: macb: Set upper 32bits of DMA ring buffer
  arm64: dts: rp1: Add ethernet DT node
  arm64: dts: broadcom: Enable RP1 ethernet for Raspberry Pi 5

 .../devicetree/bindings/net/cdns,macb.yaml     |  1 +
 .../boot/dts/broadcom/bcm2712-rpi-5-b.dts      | 18 ++++++++++++++++++
 arch/arm64/boot/dts/broadcom/rp1-common.dtsi   | 16 ++++++++++++++++
 drivers/net/ethernet/cadence/macb_main.c       | 17 +++++++++++++++++
 4 files changed, 52 insertions(+)

-- 
2.47.0

[PATCH 1/5] net: cadence: macb: Set upper 32bits of DMA ring buffer

[Stanimir Varbanov]

In case of rx queue reset and 64bit capable hardware, set the upper
32bits of DMA ring buffer address.

Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>
---
 drivers/net/ethernet/cadence/macb_main.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
index ce95fad8cedd..41c0cbb5262e 100644
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -1635,6 +1635,11 @@ static int macb_rx(struct macb_queue *queue, struct napi_struct *napi,
 
 		macb_init_rx_ring(queue);
 		queue_writel(queue, RBQP, queue->rx_ring_dma);
+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
+		if (bp->hw_dma_cap & HW_DMA_CAP_64B)
+			macb_writel(bp, RBQPH,
+				    upper_32_bits(queue->rx_ring_dma));
+#endif
 
 		macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
 
-- 
2.47.0

[PATCH 2/5] dt-bindings: net: cdns,macb: Add compatible for Raspberry Pi RP1

[Stanimir Varbanov]

From: Dave Stevenson <dave.stevenson@raspberrypi.com>

The Raspberry Pi RP1 chip has the Cadence GEM ethernet
controller, so add a compatible string for it.

Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>
---
 Documentation/devicetree/bindings/net/cdns,macb.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/net/cdns,macb.yaml b/Documentation/devicetree/bindings/net/cdns,macb.yaml
index 559d0f733e7e..0591da97d434 100644
--- a/Documentation/devicetree/bindings/net/cdns,macb.yaml
+++ b/Documentation/devicetree/bindings/net/cdns,macb.yaml
@@ -54,6 +54,7 @@ properties:
           - cdns,np4-macb             # NP4 SoC devices
           - microchip,sama7g5-emac    # Microchip SAMA7G5 ethernet interface
           - microchip,sama7g5-gem     # Microchip SAMA7G5 gigabit ethernet interface
+          - raspberrypi,rp1-gem       # Raspberry Pi RP1 gigabit ethernet interface
           - sifive,fu540-c000-gem     # SiFive FU540-C000 SoC
           - cdns,emac                 # Generic
           - cdns,gem                  # Generic
-- 
2.47.0

[PATCH 3/5] net: cadence: macb: Add support for Raspberry Pi RP1 ethernet controller

[Stanimir Varbanov]

From: Dave Stevenson <dave.stevenson@raspberrypi.com>

The RP1 chip has the Cadence GEM block, but wants the tx_clock
to always run at 125MHz, in the same way as sama7g5.
Add the relevant configuration.

Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>
---
 drivers/net/ethernet/cadence/macb_main.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
index 41c0cbb5262e..d3d5fcd42c30 100644
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -5136,6 +5136,17 @@ static const struct macb_config versal_config = {
 	.usrio = &macb_default_usrio,
 };
 
+static const struct macb_config raspberrypi_rp1_config = {
+	.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_CLK_HW_CHG |
+		MACB_CAPS_JUMBO |
+		MACB_CAPS_GEM_HAS_PTP,
+	.dma_burst_length = 16,
+	.clk_init = macb_clk_init,
+	.init = macb_init,
+	.usrio = &macb_default_usrio,
+	.jumbo_max_len = 10240,
+};
+
 static const struct of_device_id macb_dt_ids[] = {
 	{ .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
 	{ .compatible = "cdns,macb" },
@@ -5156,6 +5167,7 @@ static const struct of_device_id macb_dt_ids[] = {
 	{ .compatible = "microchip,mpfs-macb", .data = &mpfs_config },
 	{ .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config },
 	{ .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config },
+	{ .compatible = "raspberrypi,rp1-gem", .data = &raspberrypi_rp1_config },
 	{ .compatible = "xlnx,zynqmp-gem", .data = &zynqmp_config},
 	{ .compatible = "xlnx,zynq-gem", .data = &zynq_config },
 	{ .compatible = "xlnx,versal-gem", .data = &versal_config},
-- 
2.47.0

[PATCH 4/5] arm64: dts: rp1: Add ethernet DT node

[Stanimir Varbanov]

Add macb GEM ethernet DT node.

Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>
---
 arch/arm64/boot/dts/broadcom/rp1-common.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/broadcom/rp1-common.dtsi b/arch/arm64/boot/dts/broadcom/rp1-common.dtsi
index 5002a375eb0b..6bdc304c5f24 100644
--- a/arch/arm64/boot/dts/broadcom/rp1-common.dtsi
+++ b/arch/arm64/boot/dts/broadcom/rp1-common.dtsi
@@ -39,4 +39,20 @@ rp1_gpio: pinctrl@400d0000 {
 			     <1 IRQ_TYPE_LEVEL_HIGH>,
 			     <2 IRQ_TYPE_LEVEL_HIGH>;
 	};
+
+	rp1_eth: ethernet@40100000 {
+		compatible = "raspberrypi,rp1-gem";
+		reg = <0x00 0x40100000  0x0 0x4000>;
+		interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&rp1_clocks RP1_CLK_SYS>,
+			 <&rp1_clocks RP1_CLK_SYS>,
+			 <&rp1_clocks RP1_CLK_ETH>,
+			 <&rp1_clocks RP1_CLK_ETH_TSU>;
+		clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
+		local-mac-address = [00 00 00 00 00 00];
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
 };
-- 
2.47.0

[PATCH 5/5] arm64: dts: broadcom: Enable RP1 ethernet for Raspberry Pi 5

[Stanimir Varbanov]

Enable RP1 ethernet DT node for Raspberry Pi 5.

Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>
---
 .../boot/dts/broadcom/bcm2712-rpi-5-b.dts      | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
index a70a9b158df3..c70d1cb7f3b6 100644
--- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
+++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
@@ -23,3 +23,21 @@ &pcie1 {
 &pcie2 {
 	status = "okay";
 };
+
+&rp1_eth {
+	status = "okay";
+	phy-mode = "rgmii-id";
+	phy-handle = <&phy1>;
+
+	mdio {
+		reg = <0x1>;
+		reset-gpios = <&rp1_gpio 32 GPIO_ACTIVE_LOW>;
+		reset-delay-us = <5000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy1: ethernet-phy@1 {
+			reg = <0x1>;
+		};
+	};
+};
-- 
2.47.0

Re: [PATCH 1/5] net: cadence: macb: Set upper 32bits of DMA ring buffer

[Andrew Lunn]

On Fri, Aug 15, 2025 at 04:59:07PM +0300, Stanimir Varbanov wrote:
> In case of rx queue reset and 64bit capable hardware, set the upper
> 32bits of DMA ring buffer address.
> 
> Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH 3/5] net: cadence: macb: Add support for Raspberry Pi RP1 ethernet controller

[Andrew Lunn]

On Fri, Aug 15, 2025 at 04:59:09PM +0300, Stanimir Varbanov wrote:
> From: Dave Stevenson <dave.stevenson@raspberrypi.com>
> 
> The RP1 chip has the Cadence GEM block, but wants the tx_clock
> to always run at 125MHz, in the same way as sama7g5.
> Add the relevant configuration.
> 
> Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
> Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH 2/5] dt-bindings: net: cdns,macb: Add compatible for Raspberry Pi RP1

[Andrew Lunn]

On Fri, Aug 15, 2025 at 04:59:08PM +0300, Stanimir Varbanov wrote:
> From: Dave Stevenson <dave.stevenson@raspberrypi.com>
> 
> The Raspberry Pi RP1 chip has the Cadence GEM ethernet
> controller, so add a compatible string for it.
> 
> Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
> Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH 4/5] arm64: dts: rp1: Add ethernet DT node

[Andrew Lunn]

On Fri, Aug 15, 2025 at 04:59:10PM +0300, Stanimir Varbanov wrote:
> Add macb GEM ethernet DT node.
> 
> Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH 5/5] arm64: dts: broadcom: Enable RP1 ethernet for Raspberry Pi 5

[Andrew Lunn]

On Fri, Aug 15, 2025 at 04:59:11PM +0300, Stanimir Varbanov wrote:
> Enable RP1 ethernet DT node for Raspberry Pi 5.
> 
> Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH 2/5] dt-bindings: net: cdns,macb: Add compatible for Raspberry Pi RP1

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 418 bytes --]

On Fri, Aug 15, 2025 at 04:59:08PM +0300, Stanimir Varbanov wrote:
> From: Dave Stevenson <dave.stevenson@raspberrypi.com>
> 
> The Raspberry Pi RP1 chip has the Cadence GEM ethernet
> controller, so add a compatible string for it.
> 
> Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
> Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

[-- Attachment #2: signature.asc --]
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Re: [PATCH 0/5] Add ethernet support for RPi5

[Florian Fainelli]

On 8/15/25 06:59, Stanimir Varbanov wrote:
> Hello,
> 
> Few patches to enable support of ethernet on RPi5.
> 
>   - first patch is setting upper 32bits of DMA RX ring buffer in case of
>     RX queue corruption.
>   - second patch is adding a new compatible in cdns,macb yaml document
>   - third patch adds compatible and configuration for raspberrypi,rp1-gem
>   - forth and fifth patches are adding and enabling ethernet DT node on
>     RPi5.
> 
> Comments are welcome!

netdev maintainers, do you mind if I take patches 2, 4 and 5 via the 
Broadcom ARM SoC tree to avoid generating conflicts down the road? You 
can take patches 1 and 3. Thanks
-- 
Florian

Re: [PATCH 0/5] Add ethernet support for RPi5

[Jakub Kicinski]

On Mon, 18 Aug 2025 11:02:15 -0700 Florian Fainelli wrote:
> > Few patches to enable support of ethernet on RPi5.
> > 
> >   - first patch is setting upper 32bits of DMA RX ring buffer in case of
> >     RX queue corruption.
> >   - second patch is adding a new compatible in cdns,macb yaml document
> >   - third patch adds compatible and configuration for raspberrypi,rp1-gem
> >   - forth and fifth patches are adding and enabling ethernet DT node on
> >     RPi5.
> > 
> > Comments are welcome!  
> 
> netdev maintainers, do you mind if I take patches 2, 4 and 5 via the 
> Broadcom ARM SoC tree to avoid generating conflicts down the road? You 
> can take patches 1 and 3. Thanks

4, 5 make perfect sense, why patch 2? We usually take bindings.

Re: [PATCH 0/5] Add ethernet support for RPi5

[Florian Fainelli]

On 8/18/25 11:50, Jakub Kicinski wrote:
> On Mon, 18 Aug 2025 11:02:15 -0700 Florian Fainelli wrote:
>>> Few patches to enable support of ethernet on RPi5.
>>>
>>>    - first patch is setting upper 32bits of DMA RX ring buffer in case of
>>>      RX queue corruption.
>>>    - second patch is adding a new compatible in cdns,macb yaml document
>>>    - third patch adds compatible and configuration for raspberrypi,rp1-gem
>>>    - forth and fifth patches are adding and enabling ethernet DT node on
>>>      RPi5.
>>>
>>> Comments are welcome!
>>
>> netdev maintainers, do you mind if I take patches 2, 4 and 5 via the
>> Broadcom ARM SoC tree to avoid generating conflicts down the road? You
>> can take patches 1 and 3. Thanks
> 
> 4, 5 make perfect sense, why patch 2? We usually take bindings.

Because that way when CI runs against the ARM SoC tree, we don't get 
errors that the bindings are undocumented.
-- 
Florian

Re: [PATCH 0/5] Add ethernet support for RPi5

[Jakub Kicinski]

On Mon, 18 Aug 2025 11:52:28 -0700 Florian Fainelli wrote:
> On 8/18/25 11:50, Jakub Kicinski wrote:
> > On Mon, 18 Aug 2025 11:02:15 -0700 Florian Fainelli wrote:  
> >> netdev maintainers, do you mind if I take patches 2, 4 and 5 via the
> >> Broadcom ARM SoC tree to avoid generating conflicts down the road? You
> >> can take patches 1 and 3. Thanks  
> > 
> > 4, 5 make perfect sense, why patch 2? We usually take bindings.  
> 
> Because that way when CI runs against the ARM SoC tree, we don't get 
> errors that the bindings are undocumented.

Hm, my understanding is that validation should use bindings from
linux-next.. tho I'm not 100% sure. Perhaps DT maintainers can
clarify. This problem exists for all DT changes, unless there's
something exceptional about the patches I'd rather follow the default
process.

Re: [PATCH 1/5] net: cadence: macb: Set upper 32bits of DMA ring buffer

[Nicolas Ferre]

On 15/08/2025 at 15:59, Stanimir Varbanov wrote:
> In case of rx queue reset and 64bit capable hardware, set the upper
> 32bits of DMA ring buffer address.

Very nice finding! Thanks.

> Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>

A "Fixes" tag might be interesting here.

> ---
>   drivers/net/ethernet/cadence/macb_main.c | 5 +++++
>   1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
> index ce95fad8cedd..41c0cbb5262e 100644
> --- a/drivers/net/ethernet/cadence/macb_main.c
> +++ b/drivers/net/ethernet/cadence/macb_main.c
> @@ -1635,6 +1635,11 @@ static int macb_rx(struct macb_queue *queue, struct napi_struct *napi,
> 
>                  macb_init_rx_ring(queue);
>                  queue_writel(queue, RBQP, queue->rx_ring_dma);

For the sake of consistency, I would add lower_32_bits() to this call, 
as I see it for each use of RBQP or TBQP.

> +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
> +               if (bp->hw_dma_cap & HW_DMA_CAP_64B)
> +                       macb_writel(bp, RBQPH,
> +                                   upper_32_bits(queue->rx_ring_dma));
> +#endif
> 
>                  macb_writel(bp, NCR, ctrl | MACB_BIT(RE));

Best regards,
   Nicolas

Re: [PATCH 1/5] net: cadence: macb: Set upper 32bits of DMA ring buffer

[Stanimir Varbanov]

Hi Nicolas,

Thank you for the review!

On 8/19/25 11:29 AM, Nicolas Ferre wrote:
> On 15/08/2025 at 15:59, Stanimir Varbanov wrote:
>> In case of rx queue reset and 64bit capable hardware, set the upper
>> 32bits of DMA ring buffer address.
> 
> Very nice finding! Thanks.

Hmm, that reminds me that I have to update the patch body because the
credits should go to Jonathan Bell and Phil Elwell if I decipher
properly the description in raspberrypi downstream kernel :)

> 
>> Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>
> 
> A "Fixes" tag might be interesting here.

Sure, I'll do that.

> 
>> ---
>>   drivers/net/ethernet/cadence/macb_main.c | 5 +++++
>>   1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/
>> ethernet/cadence/macb_main.c
>> index ce95fad8cedd..41c0cbb5262e 100644
>> --- a/drivers/net/ethernet/cadence/macb_main.c
>> +++ b/drivers/net/ethernet/cadence/macb_main.c
>> @@ -1635,6 +1635,11 @@ static int macb_rx(struct macb_queue *queue,
>> struct napi_struct *napi,
>>
>>                  macb_init_rx_ring(queue);
>>                  queue_writel(queue, RBQP, queue->rx_ring_dma);
> 
> For the sake of consistency, I would add lower_32_bits() to this call,
> as I see it for each use of RBQP or TBQP.

Ack.

> 
>> +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
>> +               if (bp->hw_dma_cap & HW_DMA_CAP_64B)
>> +                       macb_writel(bp, RBQPH,
>> +                                   upper_32_bits(queue->rx_ring_dma));
>> +#endif
>>
>>                  macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
> 
> Best regards,
>   Nicolas
> 

regards,
~Stan

Re: [PATCH 1/5] net: cadence: macb: Set upper 32bits of DMA ring buffer

[Stanimir Varbanov]

Hi Nicolas,

On 8/19/25 11:29 AM, Nicolas Ferre wrote:
> On 15/08/2025 at 15:59, Stanimir Varbanov wrote:
>> In case of rx queue reset and 64bit capable hardware, set the upper
>> 32bits of DMA ring buffer address.
> 
> Very nice finding! Thanks.
> 
>> Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>
> 
> A "Fixes" tag might be interesting here.

Looks like the commit is:

9ba723b081a2d ("net: macb: remove BUG_ON() and reset the queue to handle
RX errors")


> 
>> ---
>>   drivers/net/ethernet/cadence/macb_main.c | 5 +++++
>>   1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/
>> ethernet/cadence/macb_main.c
>> index ce95fad8cedd..41c0cbb5262e 100644
>> --- a/drivers/net/ethernet/cadence/macb_main.c
>> +++ b/drivers/net/ethernet/cadence/macb_main.c
>> @@ -1635,6 +1635,11 @@ static int macb_rx(struct macb_queue *queue,


Also, the patch-set is adding a GEM variant but current patch is fixing
MACB. Could you please help us with testing on MACB and provide Tested-by?

>> struct napi_struct *napi,
>>
>>                  macb_init_rx_ring(queue);
>>                  queue_writel(queue, RBQP, queue->rx_ring_dma);
> 
> For the sake of consistency, I would add lower_32_bits() to this call,
> as I see it for each use of RBQP or TBQP.
> 
>> +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
>> +               if (bp->hw_dma_cap & HW_DMA_CAP_64B)
>> +                       macb_writel(bp, RBQPH,
>> +                                   upper_32_bits(queue->rx_ring_dma));
>> +#endif
>>
>>                  macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
> 
> Best regards,
>   Nicolas
> 

regards,
~Stan