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Thu, 13 Mar 2025 18:07:09 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 9EAC94002D; Thu, 13 Mar 2025 18:05:58 +0100 (CET) Received: from Webmail-eu.st.com (eqndag1node6.st.com [10.75.129.135]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id C1DE757D4E3; Thu, 13 Mar 2025 18:04:27 +0100 (CET) Received: from SAFDAG1NODE1.st.com (10.75.90.17) by EQNDAG1NODE6.st.com (10.75.129.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 13 Mar 2025 18:04:27 +0100 Received: from [10.48.86.222] (10.48.86.222) by SAFDAG1NODE1.st.com (10.75.90.17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 13 Mar 2025 18:04:26 +0100 Message-ID: Date: Thu, 13 Mar 2025 18:04:25 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 4/8] clocksource: stm32-lptimer: add support for stm32mp25 To: Daniel Lezcano , , , , , , , , CC: , , , , , , , , , References: <20250305094935.595667-1-fabrice.gasnier@foss.st.com> <20250305094935.595667-5-fabrice.gasnier@foss.st.com> <83283a94-6833-4d7d-8d89-6ba42b43b96c@linaro.org> Content-Language: en-US From: Fabrice Gasnier In-Reply-To: <83283a94-6833-4d7d-8d89-6ba42b43b96c@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.48.86.222] X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SAFDAG1NODE1.st.com (10.75.90.17) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-13_08,2025-03-11_02,2024-11-22_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250313_100737_003595_1DEA1318 X-CRM114-Status: GOOD ( 21.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 3/7/25 16:12, Daniel Lezcano wrote: > On 05/03/2025 10:49, Fabrice Gasnier wrote: >> On stm32mp25, DIER (former IER) must only be modified when the lptimer >> is enabled. On earlier SoCs, it must be only be modified when it is >> disabled. Read the LPTIM_VERR register to properly manage the enable >> state, before accessing IER. >> >> Signed-off-by: Patrick Delaunay >> Signed-off-by: Fabrice Gasnier >> --- >> Changes in V2: >> - rely on fallback compatible as no specific .data is associated to the >>    driver. Use version data from MFD core. >> - Added interrupt enable register access update in (missed in V1) >> --- >>   drivers/clocksource/timer-stm32-lp.c | 26 ++++++++++++++++++++++---- >>   1 file changed, 22 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/clocksource/timer-stm32-lp.c >> b/drivers/clocksource/timer-stm32-lp.c >> index a4c95161cb22..96d975adf7a4 100644 >> --- a/drivers/clocksource/timer-stm32-lp.c >> +++ b/drivers/clocksource/timer-stm32-lp.c >> @@ -25,6 +25,7 @@ struct stm32_lp_private { >>       struct clock_event_device clkevt; >>       unsigned long period; >>       struct device *dev; >> +    bool ier_wr_enabled;    /* Enables LPTIMER before writing into >> IER register */ >>   }; >>     static struct stm32_lp_private* >> @@ -37,8 +38,15 @@ static int stm32_clkevent_lp_shutdown(struct >> clock_event_device *clkevt) >>   { >>       struct stm32_lp_private *priv = to_priv(clkevt); >>   -    regmap_write(priv->reg, STM32_LPTIM_CR, 0); >> +    /* Disable LPTIMER either before or after writing IER register >> (else, keep it enabled) */ >> +    if (!priv->ier_wr_enabled) >> +        regmap_write(priv->reg, STM32_LPTIM_CR, 0); >> + >>       regmap_write(priv->reg, STM32_LPTIM_IER, 0); >> + > > Why not encapsulate the function ? > >     regmap_write_ier(struct stm32_lp_private *priv, int value) >     { > >         /* A comment ... */ >         if (!priv->ier_wr_enabled) >             regmap_write(priv->reg, STM32_LPTIM_CR, 0); > >         regmap_write(priv->reg, STM32_LPTIM_IER, value); > >         if (!priv->ier_wr_enabled) >             regmap_write(priv->reg, STM32_LPTIM_CR, STM32_LPTIM_ENABLE); >     } Hi Daniel, Thanks for your suggestion. I've tried various factorization but can't really find something pretty and easy to read. I think I'll rather implement some dedicated ops in V4, for stm32mp25, based on compatible data. This would allow straight forward sequence, without dangling with enable bit / flags. I also need to add some checks on new status flags. So this will avoid to add complexity on existing routines. Best Regards, Fabrice > > >> +    if (priv->ier_wr_enabled) >> +        regmap_write(priv->reg, STM32_LPTIM_CR, 0); >> + > >>       /* clear pending flags */ >>       regmap_write(priv->reg, STM32_LPTIM_ICR, STM32_LPTIM_ARRMCF); >>   @@ -51,12 +59,21 @@ static int stm32_clkevent_lp_set_timer(unsigned >> long evt, >>   { >>       struct stm32_lp_private *priv = to_priv(clkevt); >>   -    /* disable LPTIMER to be able to write into IER register*/ >> -    regmap_write(priv->reg, STM32_LPTIM_CR, 0); >> +    if (!priv->ier_wr_enabled) { >> +        /* Disable LPTIMER to be able to write into IER register */ >> +        regmap_write(priv->reg, STM32_LPTIM_CR, 0); >> +    } else { >> +        /* Enable LPTIMER to be able to write into IER register */ >> +        regmap_write(priv->reg, STM32_LPTIM_CR, STM32_LPTIM_ENABLE); >> +    } >> + >>       /* enable ARR interrupt */ >>       regmap_write(priv->reg, STM32_LPTIM_IER, STM32_LPTIM_ARRMIE); >> + >>       /* enable LPTIMER to be able to write into ARR register */ >> -    regmap_write(priv->reg, STM32_LPTIM_CR, STM32_LPTIM_ENABLE); >> +    if (!priv->ier_wr_enabled) >> +        regmap_write(priv->reg, STM32_LPTIM_CR, STM32_LPTIM_ENABLE); >> + >>       /* set next event counter */ >>       regmap_write(priv->reg, STM32_LPTIM_ARR, evt); >>   @@ -151,6 +168,7 @@ static int stm32_clkevent_lp_probe(struct >> platform_device *pdev) >>           return -ENOMEM; >>         priv->reg = ddata->regmap; >> +    priv->ier_wr_enabled = ddata->version == STM32_LPTIM_VERR_23; >>       ret = clk_prepare_enable(ddata->clk); >>       if (ret) >>           return -EINVAL; > >