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Sun, 20 Feb 2022 15:21:16 +0000 MIME-Version: 1.0 Date: Sun, 20 Feb 2022 15:21:15 +0000 From: Marc Zyngier To: "Russell King (Oracle)" Cc: Barry Song <21cnbao@gmail.com>, tglx@linutronix.de, will@kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxarm@huawei.com, Barry Song Subject: Re: [PATCH] irqchip/gic-v3: use dsb(ishst) to synchronize data to smp before issuing ipi In-Reply-To: References: <20220218215549.4274-1-song.bao.hua@hisilicon.com> User-Agent: Roundcube Webmail/1.4.13 Message-ID: X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: linux@armlinux.org.uk, 21cnbao@gmail.com, tglx@linutronix.de, will@kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxarm@huawei.com, song.bao.hua@hisilicon.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220220_072120_182667_58FBA937 X-CRM114-Status: GOOD ( 18.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2022-02-20 15:04, Russell King (Oracle) wrote: > On Sat, Feb 19, 2022 at 05:55:49AM +0800, Barry Song wrote: >> dsb(ishst) should be enough here as we only need to guarantee the >> visibility of data to other CPUs in smp inner domain before we >> send the ipi. >> >> Signed-off-by: Barry Song >> --- >> drivers/irqchip/irq-gic-v3.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/irqchip/irq-gic-v3.c >> b/drivers/irqchip/irq-gic-v3.c >> index 5e935d97207d..0efe1a9a9f3b 100644 >> --- a/drivers/irqchip/irq-gic-v3.c >> +++ b/drivers/irqchip/irq-gic-v3.c >> @@ -1211,7 +1211,7 @@ static void gic_ipi_send_mask(struct irq_data >> *d, const struct cpumask *mask) >> * Ensure that stores to Normal memory are visible to the >> * other CPUs before issuing the IPI. >> */ >> - wmb(); >> + dsb(ishst); > > On ARM, wmb() is a dsb(st) followed by other operations which may > include a sync operation at the L2 cache, and SoC specific barriers > for the bus. Hopefully, nothing will break if the sledge hammer is > replaced by the tack hammer. The saving grace is that ARMv8 forbids (as per D4.4.11) these SW-visible, non architected caches (something like PL310 simply isn't allowed). Given that GICv3 requires ARMv8 the first place, we should be OK. As for SoC-specific bus barriers, I don't know of any that would affect an ARMv8 based SoC. But I'm always prepared to be badly surprised... M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel