From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7B77CCEDDB1 for ; Thu, 10 Oct 2024 01:50:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:MIME-Version:Date:Message-ID:From:References:CC:To: Subject:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=4KscyJIM558NlwVNXAYO6EbC46blpuLtW0oKEifL9xI=; b=N5kXIc57U0v2IMC0Kw0sp4/Hzz dcSC4lq2hr4ghbqDrf2kuEyFrTiCzEd+shW/0oD1DfGhkSgfx8VAJZvqYV1NnwVzsTbIB5PeKEWq0 8MDnYhzYoL2kojwm9ix7/MbBRFXhw6VcEK3k+moXLtNDyIOzQwv7enrTCLal9fYH92dnQDRdOtptO /S0QE3X3eB7kDwYfJSsTiMV8sn3/xppNmskwP2JfiLdn2asJX+PuEI+iZDcW9TrX/ckiw7PVFoj+G 5eFU6u5Sigi3C3BlXuQ8TkEPdq8kIGws2xBVC+sjaUyRw3q3+XKOC0Jearx6yET+jnrxbO4KZMj/I VfFEwnVA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1syiJy-0000000BFLi-2UZJ; Thu, 10 Oct 2024 01:50:30 +0000 Received: from szxga07-in.huawei.com ([45.249.212.35]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1syiIc-0000000BFGP-3a7t for linux-arm-kernel@lists.infradead.org; Thu, 10 Oct 2024 01:49:08 +0000 Received: from mail.maildlp.com (unknown [172.19.88.163]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4XPCLt2fhFz1SCQ3; Thu, 10 Oct 2024 09:47:50 +0800 (CST) Received: from dggpemf500002.china.huawei.com (unknown [7.185.36.57]) by mail.maildlp.com (Postfix) with ESMTPS id 0795E18001B; Thu, 10 Oct 2024 09:48:57 +0800 (CST) Received: from [10.174.178.247] (10.174.178.247) by dggpemf500002.china.huawei.com (7.185.36.57) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Thu, 10 Oct 2024 09:48:55 +0800 Subject: Re: [PATCH v3 2/9] ACPICA: IORT: Update for revision E.f To: Jason Gunthorpe , , , Joerg Roedel , Kevin Tian , , Len Brown , , , Lorenzo Pieralisi , "Rafael J. Wysocki" , Robert Moore , Robin Murphy , Sudeep Holla , Will Deacon CC: Alex Williamson , Eric Auger , Jean-Philippe Brucker , Moritz Fischer , Michael Shavit , Nicolin Chen , , "Rafael J. Wysocki" , Shameerali Kolothum Thodi , Mostafa Saleh References: <2-v3-e2e16cd7467f+2a6a1-smmuv3_nesting_jgg@nvidia.com> From: Hanjun Guo Message-ID: Date: Thu, 10 Oct 2024 09:48:55 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:68.0) Gecko/20100101 Thunderbird/68.6.0 MIME-Version: 1.0 In-Reply-To: <2-v3-e2e16cd7467f+2a6a1-smmuv3_nesting_jgg@nvidia.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Originating-IP: [10.174.178.247] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To dggpemf500002.china.huawei.com (7.185.36.57) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241009_184907_172066_6480945A X-CRM114-Status: GOOD ( 11.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2024/10/10 0:23, Jason Gunthorpe wrote: > From: Nicolin Chen > > ACPICA commit c4f5c083d24df9ddd71d5782c0988408cf0fc1ab > > The IORT spec, Issue E.f (April 2024), adds a new CANWBS bit to the Memory > Access Flag field in the Memory Access Properties table, mainly for a PCI > Root Complex. > > This CANWBS defines the coherency of memory accesses to be not marked IOWB > cacheable/shareable. Its value further implies the coherency impact from a > pair of mismatched memory attributes (e.g. in a nested translation case): > 0x0: Use of mismatched memory attributes for accesses made by this > device may lead to a loss of coherency. > 0x1: Coherency of accesses made by this device to locations in > Conventional memory are ensured as follows, even if the memory > attributes for the accesses presented by the device or provided by > the SMMU are different from Inner and Outer Write-back cacheable, > Shareable. > Acked-by: Hanjun Guo Thanks Hanjun