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[85.68.201.192]) by smtp.gmail.com with ESMTPSA id c10-20020a5d4cca000000b0024278304ef6sm1498230wrt.13.2022.12.15.23.28.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 Dec 2022 23:28:28 -0800 (PST) Message-ID: Date: Fri, 16 Dec 2022 08:28:26 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH v7 1/6] DONOTMERGE: arm64: dts: ti: Add TI TPS65219 PMIC support for AM642 SK board. Content-Language: en-US To: Vignesh Raghavendra , Nishanth Menon , Mark Brown Cc: Wadim Egorov , "lgirdwood@gmail.com" , "robh+dt@kernel.org" , "kristo@kernel.org" , "dmitry.torokhov@gmail.com" , "krzysztof.kozlowski+dt@linaro.org" , "catalin.marinas@arm.com" , "will@kernel.org" , "lee@kernel.org" , "tony@atomide.com" , "shawnguo@kernel.org" , "geert+renesas@glider.be" , "dmitry.baryshkov@linaro.org" , "marcel.ziswiler@toradex.com" , "vkoul@kernel.org" , "biju.das.jz@bp.renesas.com" , "arnd@arndb.de" , "jeff@labundy.com" , "afd@ti.com" , "khilman@baylibre.com" , "narmstrong@baylibre.com" , "msp@baylibre.com" , "j-keerthy@ti.com" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-input@vger.kernel.org" , "linux-omap@vger.kernel.org" References: <20221104152311.1098603-1-jneanne@baylibre.com> <20221104152311.1098603-2-jneanne@baylibre.com> <20221215175411.znxy3d6ussq2iq5h@grieving> <20221215214149.whcjdphxxvvedrih@affront> From: jerome Neanne In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221215_232832_610466_8496D54C X-CRM114-Status: GOOD ( 18.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 16/12/2022 07:21, Vignesh Raghavendra wrote: > > > On 16/12/22 03:11, Nishanth Menon wrote: >> On 18:22-20221215, Mark Brown wrote: >>> On Thu, Dec 15, 2022 at 11:54:11AM -0600, Nishanth Menon wrote: >>>> On 16:09-20221215, Mark Brown wrote: >>> >>>>> That proposal looks really non-idiomatic and quite unusual, if there's a >>>>> fixed voltage supply to the LDO I'd expect to see it modeled as a fixed >>>>> voltage regulator. I'm not sure what the use of bypass here is trying >>>>> to accomplish TBH. >>> >>>> The problem is this - the default NVM in the PMIC is setup such that >>>> VSET value =3.3v and bypass bit set (makes sense since the vin=3.3v). >>> >>> This implies no voltage drop over the LDO? Sounds a bit suspect. >> >> Not the choice I'd probably have made ;) >> >>> >>>> Now the constraint is bypass bit cannot be changed without the LDO >>>> being switched off. >>> > > Per https://www.ti.com/lit/ds/symlink/tps65219.pdf (7.3.6 Linear > Regulators). > > LDOs have two modes: > > 1. Load switch mode: in this case, output voltages of 1.5V up to 5.5V > are supported. > > 2 Linear regulator LDO mode where output voltage is programmable in the > range of 0.6V to 3.4V in 50mV-steps with possibility of bypass. > > (CAUTION on page 25): > A mode change between LDO(/bypass) and LSW-mode must only be performed, > when this regulator is disabled! > A change between LDO and bypass-mode (supported by LDO1 and LDO2 only) > is supported during operation. > > So, seems like bypass can be toggled even with LDO on? >I possibly miss-interpreted this caution statement which leads to that situation. Your understanding sounds correct. My mistake... Sorry for that Regards, Jerome. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel